公开(公告)号：WO1994018670A1

公开(公告)日：1994-08-18

申请号：PCT/US1994001084

申请日：1994-01-31

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  BEHRENS, Richard, T. ,  ANDERSON, Kent, D. ,  ARMSTRONG, Alan ,  DUDLEY, Trent ,  FOLAND, Bill ,  GLOVER, Neal ,  KING, Larry

IPC: G11B05/09

CPC classification number: G11B20/10055 ,  G11B5/012 ,  G11B5/09 ,  G11B20/10 ,  G11B20/10009 ,  G11B20/1258 ,  G11B20/1403 ,  G11B20/1426 ,  G11B20/18 ,  G11B27/3027 ,  G11B2020/1476 ,  H03M13/31

Abstract: A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control (32), timing recovery (34), sequence detection (40), RLL (1, 7) encoding (48) and RLL (1, 7) decoding (28), and channel quality measurement (46) is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection (40). These characteristics, together with error-tolerant sync mark detection (26) and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery.

Abstract translation: 具有提供数字增益控制（32），定时恢复（34），序列检测（40），RLL（1,7）编码（48）和RLL（1,7）的单芯片集成电路数字部分的同步读通道， 解码（28）和信道质量测量（46）。 集成电路既适用于中心采样和侧采样，又具有各种脉冲整形和恢复参数的高度可编程性，以及使用序列检测提供解码数据的能力（40）。 这些特性以及容错同步标记检测（26）以及当同步标记被消除时恢复数据的能力允许各种各样的重试和恢复策略来最大限度地提高数据恢复的可能性。

公开(公告)号：EP0746848A1

公开(公告)日：1996-12-11

申请号：EP94909516.0

申请日：1994-01-31

Applicant: CIRRUS LOGIC, INC.

Inventor： BEHRENS, Richard, T. ,  ANDERSON, Kent, D. ,  ARMSTRONG, Alan ,  DUDLEY, Trent ,  FOLAND, Bill ,  GLOVER, Neal ,  KING, Larry

IPC: G11B5 ,  G11B20 ,  G11B27 ,  H03M13

CPC classification number: G11B20/10055 ,  G11B5/012 ,  G11B5/09 ,  G11B20/10 ,  G11B20/10009 ,  G11B20/1258 ,  G11B20/1403 ,  G11B20/1426 ,  G11B20/18 ,  G11B27/3027 ,  G11B2020/1476 ,  H03M13/31

Abstract: A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control (32), timing recovery (34), sequence detection (40), RLL (1, 7) encoding (48) and RLL (1, 7) decoding (28), and channel quality measurement (46) is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection (40). These characteristics, together with error-tolerant sync mark detection (26) and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery.