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公开(公告)号：DE732830T1
公开(公告)日：1999-08-19
申请号：DE96103852
申请日：1996-03-12
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： BURZIO MARCO
Abstract: The circuit for clock signal extraction from a high speed data stream allows a rapid attainment of the identity between the frequencies of the locally generated clock signal and of the data signal, even when such frequencies are very different. The circuit can easily be inserted into a more complex CMOS digital integrated circuit, it has low power dissipation and is capable of operating at bit rates exceeding 300 Mbit/s. The circuit comprises a main phase locked loop, which controls a voltage controlled oscillator by continually controlling its phase, and a secondary loop, which allows the main loop to become locked, by causing the voltage controlled oscillator to oscillate at a frequency close to the operating frequency.
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公开(公告)号：IT1293460B1
公开(公告)日：1999-03-01
申请号：ITTO970647
申请日：1997-07-17
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： BURZIO MARCO , RICCHIUTO SAVERIO
IPC: H04B20060101
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公开(公告)号：IT1284718B1
公开(公告)日：1998-05-21
申请号：ITTO960665
申请日：1996-07-31
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： BOSTICA BRUNO , BURZIO MARCO , PELLEGRINO PAOLO
Abstract: A device and a method for aligning in time two essentially isochronous digital signals are provided, in which a plurality (2 ) of replicas (CK1-CK4) of the first signal (CKIN), separated by a given phase difference, are generated and a number of said replicas (CK3, CK4) is subjected to sampling (4, 5) in correspondence with the rising edges of the second signal (DATA). As the result of the sampling, a combination of logic signals (SLO, SL1) is obtained which is representative of the phase relation existing between each of said replicas (CK1-CK4) and the second signal (DATA). The output signal (CKOUT) of the device, aligned with the second signal, corresponds to the one, among the replicas (CK1- CK4) of the first signal, which best reproduces the desired alignment condition.
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14.发明专利
公开(公告)号：CA2291540C
公开(公告)日：2004-06-08
申请号：CA2291540
申请日：1999-12-03
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： BURZIO MARCO , BALISTRERI EMANUELE
Abstract: A device is provided for compensating process and operating parameters variations in a CMOS integrated circuit. The device comprises means for generating a first and a second compensation signals which depend on quality indexes of the fabrication process of the P and N transistors of the integrated circuit and on the operating temperature, and which are capable of compensating deviations of the controlled quantity from the desired value, due to the deviation of the quality indexes and temperature, respectively, from a typical value which would originate the desired value for the output parameter. The compensating device also can be implemented in the form of CMOS integrated circuit, preferably jointly with the device to be subjected to compensation.
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公开(公告)号：CA2203489C
公开(公告)日：2001-07-10
申请号：CA2203489
申请日：1997-04-23
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： BOSTICA BRUNO , BURZIO MARCO , PELLEGRINO PAOLO , PESANDO LUCA
IPC: H01L27/092 , H01L21/8238 , H01S5/042 , H01S5/068 , H01S5/40 , H04B10/04 , H04B10/06 , H04B10/142 , H04B10/152 , H01S3/10
Abstract: A high speed drive circuit for optical sources. The circuit comprises bias and modulation current generators for both p-type and n-type optical sources, and a pair of control voltage sources for controlling the bias and modulation current generators, which obtain pairs of control voltages from an adjustable driving current. The circuit includes control logic and CMOS gates for selecting between the p-type and n-type generators by means of an external signal. The circuit is fabricated as an integrated circuit having three pads, one for each control voltage source and the third pad comprises the current generators, the CMOS gates and the control logic circuit.
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Patent Agency Ranking
公开(公告)号：CA2290723A1
公开(公告)日：2000-05-26
申请号：CA2290723
申请日：1999-11-25
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： BALISTRERI EMANUELE , BURZIO MARCO
IPC: H01L21/822 , H01L27/04 , H03F3/45 , H03H11/26 , H03K3/0231 , H03K3/03 , H03K3/354 , H03K5/13
Abstract: The delay element consists of a differential amplifier (M15, M8, M2, M6, M5) in which the load transistors (M2, M5) are associated to respective gate biasing transistors (M21, M22) connected in a source follower configuration, and to feedback transistors (M3, M4), which implement a negative impedance in parallel to a positive impedance represented by each of the load transistors (M2, M5). The modulation of the delay is achieved by modulating the bias currents of the load transistors (M2, M5), the feedback transistors (M3, M4) and the gate biasing transistors (M21, M22).
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公开(公告)号：ITTO981018D0
公开(公告)日：1998-12-03
申请号：ITTO981018
申请日：1998-12-03
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： BURZIO MARCO , BALISTRERI EMANUELE
IPC: H01L21/8238 , G05F3/24 , H01L27/02 , H01L27/092 , H03B5/04 , H03F1/30 , H03K19/003
Abstract: A device (DC) is provided for compensating process and operating parameters variations in a CMOS integrated circuit. The device comprises means (CP, CT) for generating a first and a second compensation signals which depend on quality indexes of the fabrication process of the P and N transistors of the integrated circuit and on the operating temperature, and which are capable of compensating deviations of the controlled quantity from the desired value, due to the deviation of the quality indexes and temperature, respectively, from a typical value which would originate the desired value for the output parameter. The compensating device also can be implemented in the form of CMOS integrated circuit, preferably jointly with the device (OS) to be subjected to compensation.
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公开(公告)号：IT1285852B1
公开(公告)日：1998-06-24
申请号：ITTO960326
申请日：1996-04-24
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： BOSTICA BRUNO , BURZIO MARCO , PELLEGRINO PAOLO , PESANDO LUCA
IPC: H01L27/092 , H01L21/8238 , H01S5/042 , H01S5/068 , H01S5/40 , H04B10/04 , H04B10/06 , H04B10/142 , H04B10/152
Abstract: The circuit comprises bias and modulation current generators (T1...T6) for both p-type and n-type optical sources, and a pair of sources of control voltages (B, M) for the bias and modulation current generators, which obtain pairs of control voltages from an adjustable driving current. An external signal allows selecting, by means of a control logic (LC) and CMOS gates (P1...P6), the generators required by the source (LA). The circuit is made by using three pads of an integrated circuit, one for each control voltage source (B, M) and the third (D) comprising the current generators (T1...T6), the CMOS gates (P1...P6) and the control logic (LC).
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公开(公告)号：ITTO960665A1
公开(公告)日：1998-02-02
申请号：ITTO960665
申请日：1996-07-31
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： BOSTICA BRUNO , BURZIO MARCO , PELLEGRINO PAOLO
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20.发明专利
公开(公告)号：CA2212292A1
公开(公告)日：1998-01-31
申请号：CA2212292
申请日：1997-07-30
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： PELLEGRINO PAOLO , BOSTICA BRUNO , BURZIO MARCO
Abstract: A device and a method for aligning in time two essentially isochronous digit al signals are provided, in which a plurality (2n) of replicas (CK1-CK4) of the first s ignal (CKIN), separated by a given phase difference, are generated and a number of said re plicas (CK3, CK4) is subjected to sampling (4, 5) in correspondence with the rising edges of the second signal (DATA). As the result of the sampling, a combination of lo gic signals (SL0, SL1) is obtained which is representative of the phase relation existin g between each of said replicas (CK1-CK4) and the second signal (DATA). The output sig nal (CKOUT) of the device, aligned with the second signal, corresponds to the on e, among the replicas (CK1-CK4) of the first signal, which best reproduces the desire d alignment condition.
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