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    DEVICE FOR AND METHOD OF ALIGNING IN TIME DIGITAL SIGNALS, FOR EXAMPLE A CLOCK SIGNAL AND A DATA STREAM
    3.
    发明专利
    DEVICE FOR AND METHOD OF ALIGNING IN TIME DIGITAL SIGNALS, FOR EXAMPLE A CLOCK SIGNAL AND A DATA STREAM 未知

    公开(公告)号：CA2212292C

    公开(公告)日：2001-10-16

    申请号：CA2212292

    申请日：1997-07-30

    Applicant: CSELT CENTRO STUDI LAB TELECOM

    Inventor： BURZIO MARCO ,  BOSTICA BRUNO ,  PELLEGRINO PAOLO

    IPC: G06F13/42 ,  H03K5/00 ,  H03K5/13 ,  H04L7/02 ,  H04L7/033

    Abstract: A device and a method for aligning in time two essentially isochronous digit al signals are provided, in which a plurality (2n) of replicas (CK1-CK4) of the first s ignal (CKIN), separated by a given phase difference, are generated and a number of said re plicas (CK3, CK4) is subjected to sampling (4, 5) in correspondence with the rising edges of the second signal (DATA). As the result of the sampling, a combination of lo gic signals (SL0, SL1) is obtained which is representative of the phase relation existin g between each of said replicas (CK1-CK4) and the second signal (DATA). The output sig nal (CKOUT) of the device, aligned with the second signal, corresponds to the on e, among the replicas (CK1-CK4) of the first signal, which best reproduces the desire d alignment condition.

    4.
    发明专利
    未知

    公开(公告)号：IT1284718B1

    公开(公告)日：1998-05-21

    申请号：ITTO960665

    申请日：1996-07-31

    Applicant: CSELT CENTRO STUDI LAB TELECOM

    Inventor： BOSTICA BRUNO ,  BURZIO MARCO ,  PELLEGRINO PAOLO

    IPC: G06F13/42 ,  H03K5/00 ,  H03K5/13 ,  H04L7/02 ,  H04L7/033

    Abstract: A device and a method for aligning in time two essentially isochronous digital signals are provided, in which a plurality (2 ) of replicas (CK1-CK4) of the first signal (CKIN), separated by a given phase difference, are generated and a number of said replicas (CK3, CK4) is subjected to sampling (4, 5) in correspondence with the rising edges of the second signal (DATA). As the result of the sampling, a combination of logic signals (SLO, SL1) is obtained which is representative of the phase relation existing between each of said replicas (CK1-CK4) and the second signal (DATA). The output signal (CKOUT) of the device, aligned with the second signal, corresponds to the one, among the replicas (CK1- CK4) of the first signal, which best reproduces the desired alignment condition.

    OPTICAL SWITCH FOR FAST CELL-SWITCHING NETWORKS
    5.
    发明专利
    OPTICAL SWITCH FOR FAST CELL-SWITCHING NETWORKS 未知

    公开(公告)号：CA2098358C

    公开(公告)日：1997-06-24

    申请号：CA2098358

    申请日：1993-06-14

    Applicant: CSELT CENTRO STUDI LAB TELECOM

    Inventor： BOSTICA BRUNO ,  CINATO PAOLA ,  DE BOSIO ALFREDO

    IPC: H04Q3/52 ,  H04L12/56 ,  H04Q11/00 ,  H04Q11/04 ,  H04J14/08

    Abstract: An optical switch for fast cell-switching networks comprises an optical interconnection network and an electrical control network. In order to fully exploit optical component capabilities and to overcome the constraints imposed by operating speed limits of electronic components, each input of the interconnection network is associated with components which form aggregates of cells which are to follow a similar path through the interconnection network and time-compress the aggregates, and each output is associated with components for the time expansion of the aggregates and separation of the aggregated cells.

    Optical Switch for Fast Cell-Switching Networks
    6.
    发明专利
    Optical Switch for Fast Cell-Switching Networks 未知

    公开(公告)号：CA2098358A1

    公开(公告)日：1993-12-16

    申请号：CA2098358

    申请日：1993-06-14

    Applicant: CSELT CENTRO STUDI LAB TELECOM

    Inventor： BOSTICA BRUNO ,  CINATO PAOLA ,  DE BOSIO ALFREDO

    IPC: H04Q3/52 ,  H04L12/56 ,  H04Q11/00 ,  H04Q11/04 ,  H04J14/08

    Abstract: The optical switch for fast cell-switching networks comprises an optical interconnection network (CM) and an electrical control network (CT). In order to fully exploit optical component capabilities and to overcome the constraints imposed by operating speed limits of electronic components, each input (IN1...INk) of the interconnection network (CM) is associated with means (PAC1...PACk) forming aggregates of cells which are to follow a same path through the interconnection network and time-compressing the aggregates, and each output (OU1...OUk) is associated with means (PAD1...PADk) for the time expansion of the aggregates and separation of the aggregate cells.

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