公开(公告)号：EP0854615A2

公开(公告)日：1998-07-22

申请号：EP97310666.9

申请日：1997-12-30

Applicant: Compaq Computer Corporation

Inventor： Walker, William J. ,  Kotzur, Gary B. ,  Witkowski, Michael L. ,  Hareski, Patricia E. ,  Mayer, Dale J.

IPC: H04L12/44 ,  H04L29/04 ,  H04L12/40 ,  H04L12/56

CPC classification number: H04L49/351 ,  H04L49/254 ,  H04L49/354

Abstract: A multiport polling system for a network switch including a plurality of network ports, each including receive and transmit buffers. Each port includes port status logic for providing status signals indicative of whether a corresponding port has received data from a network device and whether a corresponding port has available space to receive data to transmit to a network device. The network switch further includes a switch manager for controlling data flow between the ports. The switch manager includes polling logic for periodically polling the port status logic of each port for receiving the status signals, and a memory for storing values indicative of the status signals for each port. In this manner, all of the ports are simultaneously polled in a singe query and the receive and transmit status of each port is maintained in the memory. This facilitates arbitration and control logic, which continuously reviews the memory to determine when to retrieve data from a source port and when to transmit data to one or more destination ports. The ports are preferably implemented with quad cascade devices for providing multiplexed status signals.

Abstract translation: 一种用于包括多个网络端口的网络交换机的多端口轮询系统，每个网络端口包括接收和发送缓冲器。 每个端口包括端口状态逻辑，用于提供表示相应端口是否已经从网络设备接收到数据的状态信号以及对应端口是否具有用于接收数据以发送到网络设备的可用空间。 网络交换机还包括用于控制端口之间的数据流的交换管理器。 交换机管理器包括用于周期性轮询用于接收状态信号的每个端口的端口状态逻辑的轮询逻辑，以及用于存储指示每个端口的状态信号的值的存储器。 以这种方式，所有端口同时轮询单个查询，并且每个端口的接收和发送状态保持在存储器中。 这有助于仲裁和控制逻辑，其不断地检查存储器以确定何时从源端口检索数据以及何时将数据发送到一个或多个目的地端口。 这些端口优选地用用于提供多路复用状态信号的四级级联装置来实现。

公开(公告)号：EP0854612A2

公开(公告)日：1998-07-22

申请号：EP97310662.8

申请日：1997-12-30

Applicant: Compaq Computer Corporation

Inventor： Walker, William J. ,  Kotzur, Gary B. ,  Hareski, Patricia E. ,  Witkowski, Michael L. ,  Mayer, Dale J.

IPC: H04L12/44 ,  H04L29/04 ,  H04L12/40 ,  H04L12/56

CPC classification number: H04L49/351 ,  H04L49/254 ,  H04L49/354

Abstract: A system for performing concurrent read and write cycles in a network switch. The network switch includes several network ports, a data bus and a switch manager to execute a concurrent read and write cycle on the data bus by asserting a first port number to identify a source port followed by a second port number to identify a destination port. Each of the ports includes a network interface for sending and receiving data packets and a data interface to store the first port number, to assert data received from the network interface onto the data bus if that port is identified by the first port number, and to retrieve data from the data bus for transmission by the network interface if that port is identified by the second port number. In this manner, data is transferred directly between a source and a destination port without being buffered in the switch manager. The bandwidth of the data bus is increased since data is transferred only once on the data bus. Latches are provided for the ports to latch the read port number to allow that write port number to be asserted during the cycle. A method of executing a concurrent read and write cycle includes the steps of asserting a first port number to identify a source port, latching the first port number, asserting a second port number to identify a destination port, and concurrently writing and reading the data on the data bus.

Abstract translation: 一种用于在网络交换机执行并发读写周期系统。 网络交换机包括若干个网络端口，一个数据总线和一个交换机管理器来执行并行读和通过产生一个第一个端口号来识别随后的第二端口号的源端口来识别目的地端口写数据总线上的周期。 每个端口包括用于发送和接收数据分组和数据接口存储所述第一端口号，如果没有端口通过第一端口号标识断言从网络接口接收到数据总线上的数据的网络接口，以及 如果没有端口由所述第二端口号标识由网络接口​​从数据总线传输的数据。 以这种方式，数据在源和目的端口之间直接传送而无需在交换机管理器被缓冲。 由于数据在数据总线上传送的仅一旦数据总线的带宽被增加。 提供锁存器端口锁存读端口号，让没写端口号的周期中被断言。 执行并行读和写周期的方法，包括断言的第一端口号来识别源端口，锁存所述第一端口号，断言的第二端口号来识别的目的地端口，和兼写入和读取数据的步骤 数据总线。

公开(公告)号：EP0720094A2

公开(公告)日：1996-07-03

申请号：EP95309547.8

申请日：1995-12-29

Applicant: Compaq Computer Corporation

Inventor： Goodrum, Alan A. ,  Kotzur, Gary B. ,  Lantz, Kurt C. ,  Heinrich, David F. ,  Wilson, Jeffrey R.

IPC: G06F11/00 ,  G06F15/16

CPC classification number: G06F15/177 ,  G06F1/26 ,  G06F11/1417

Abstract: A hot spare boot circuit that automatically switches from a non-operational CPU to an operational CPU for powering up the computer system. In the multiprocessor computer system, a first CPU is designated to perform power on operations. If the first CPU fails, which is determined when a dead man counter in the hot spare boot circuit times out, the hot spare circuit ensures that the first CPU is in a disabled state. Next, the hot spare boot circuit identifies an operational second CPU, reinitializing certain ID information as necessary such that the second CPU can properly perform power on operations. The hot spare boot then awakens the second CPU, using a startup interprocessor interrupt in one embodiment, or simply negating the hard reset of the second CPU in a second embodiment. The second CPU then proceeds to perform the power on functions.

Abstract translation: 一个热备用引导电路，可自动从非操作CPU切换到运行CPU，以便为计算机系统供电。 在多处理器计算机系统中，指定第一CPU执行上电操作。 如果第一个CPU出现故障，当热备用引导电路中的死亡计数器超时时，该热备用电路确保第一个CPU处于禁用状态。 接下来，热备用引导电路识别操作的第二CPU，根据需要重新初始化某些ID信息，使得第二CPU可以正常地执行上电操作。 在第二实施例中，热备用引导然后唤醒第二CPU，在一个实施例中使用启动处理器中断，或简单地否定第二CPU的硬复位。 然后第二个CPU继续执行上电功能。

公开(公告)号：EP0854606B1

公开(公告)日：2004-10-27

申请号：EP97310652.9

申请日：1997-12-30

Applicant: Compaq Computer Corporation

Inventor： Hareski, Patricia E. ,  Walker, William J. ,  Kotzur, Gary B. ,  Mayer, Dale J. ,  Witkowski, Michael L.

IPC: H04L12/24 ,  H04L12/44 ,  H04L12/40 ,  H04L12/56

CPC classification number: H04L41/26 ,  H04L41/046 ,  H04L41/24 ,  H04L49/201 ,  H04L49/351 ,  H04L49/354

公开(公告)号：EP0854615A3

公开(公告)日：1999-06-16

申请号：EP97310666.9

申请日：1997-12-30

Applicant: Compaq Computer Corporation

Inventor： Walker, William J. ,  Kotzur, Gary B. ,  Witkowski, Michael L. ,  Hareski, Patricia E. ,  Mayer, Dale J.

IPC: H04L12/44 ,  H04L29/04 ,  H04L12/40 ,  H04L12/56

CPC classification number: H04L49/351 ,  H04L49/254 ,  H04L49/354

Abstract: A multiport polling system for a network switch including a plurality of network ports, each including receive and transmit buffers. Each port includes port status logic for providing status signals indicative of whether a corresponding port has received data from a network device and whether a corresponding port has available space to receive data to transmit to a network device. The network switch further includes a switch manager for controlling data flow between the ports. The switch manager includes polling logic for periodically polling the port status logic of each port for receiving the status signals, and a memory for storing values indicative of the status signals for each port. In this manner, all of the ports are simultaneously polled in a singe query and the receive and transmit status of each port is maintained in the memory. This facilitates arbitration and control logic, which continuously reviews the memory to determine when to retrieve data from a source port and when to transmit data to one or more destination ports. The ports are preferably implemented with quad cascade devices for providing multiplexed status signals.

公开(公告)号：EP0854613A3

公开(公告)日：1999-06-16

申请号：EP97310663.6

申请日：1997-12-30

Applicant: Compaq Computer Corporation

Inventor： Witkowski, Michael L. ,  Chandler, Gregory T. ,  Khan, Mohammed A. ,  Kotzur, Gary B. ,  Mayer, Dale J. ,  Walker, William J.

IPC: H04L12/44 ,  H04L12/40 ,  H04L12/46 ,  H04L12/56

CPC classification number: H04L49/351 ,  H04L49/205 ,  H04L49/354 ,  Y10S370/911

Abstract: A network switch including a plurality of first network ports, a plurality of second network ports, a first bus, a second bus and a bridge interface coupled between the first and second buses. The first ports receive and transmit network data according to a first network protocol and the second ports receive and transmit network data according to a second network protocol. The first and second buses operate according to different bus standards. The bridge interface enables data transfer between the first and second buses and thus between the networks operating at different protocols. The switch includes a switch manager that controls the flow of network data and a processor for performing supervisory and control functions. The bridge interface includes receive buffers and transmit buffers assigned to respective ports. During packet data transfer operations across the first bus, the bridge interface emulates a first network port. During packet data transfer operations across the second bus, the bridge interface primarily acts as a slave to the second network ports by storing control lists for execution by the second network ports. This processor is relieved of performing necessary overhead functions associated with the second bus and is thus freed to perform other important switch functions.

公开(公告)号：EP0910195A3

公开(公告)日：1999-05-12

申请号：EP98307556.5

申请日：1998-09-17

Applicant: Compaq Computer Corporation

Inventor： Witkowski, Michael L. ,  Mayer, Dale J. ,  Walker, William J. ,  Roller, Kirk D. ,  Hareski, Patricia E. ,  Kotzur, Gary B.

IPC: H04L12/46 ,  H04L29/00

CPC classification number: H04L12/467 ,  H04L49/201 ,  H04L49/205 ,  H04L49/254 ,  H04L49/351 ,  H04L49/354 ,  H04L69/14

Abstract: A network communication device including port control circuitry for controlling packet flow between the ports of the device, where the port control circuitry includes a port manager that directs packets between the ports and port bonding circuitry that bonds two or more ofthe ports into a bonded port set. For each packet to be sent via the bonded port set, the port bonding circuitry selects one of the bonded ports for transmitting the packet. More than one bonded port set may be defined in a given communication device, and each bonded port set may include from two ports up to all the ports of the device, as long as each port is included in only one bonded port set. One or more port bonding registers are provided to identify which ofthe plurality ofports are bonded in each bonded port set. In one embodiment, the bonded ports are selected on a packet by packet basis so as to achieve a relatively even distribution of packets sent by each bonded port. In an alternative embodiment bonded ports are assigned to packet source identifiers so as to achieve a relatively even distribution of source identifiers among the bonded ports. If bonded ports are assigned to particular source identifiers, then the traffic is preferably monitored and the assignments are periodically adjusted to achieve even distribution of packet flow on the bonded link. The bonded ports may have different bandwidths, in which case traffic is distributed on a proportionate basis.

Abstract translation: 一种网络通信设备，包括用于控制设备的端口之间的分组流的端口控制电路，其中端口控制电路包括在端口之间引导分组的端口管理器和将两个或更多个端口绑定到绑定端口集的端口绑定电路 。 对于要通过绑定端口集发送的每个分组，端口绑定电路选择一个绑定端口来发送分组。 可以在给定的通信设备中定义多于一个绑定端口组，并且每个绑定端口组可以包括从两个端口直到设备的所有端口，只要每个端口仅包含在一个绑定端口组中。 提供一个或多个端口绑定寄存器以标识在每个绑定端口组中绑定了多个端口中的哪一个。 在一个实施例中，绑定端口是逐个分组地选择的，以便实现由每个绑定端口发送的分组的相对均匀分布。 在替代实施例中，将绑定端口分配给分组源标识符，以便实现绑定端口中源标识符的相对均匀分布。 如果将绑定端口分配给特定的源标识符，则优选监视流量并周期性地调整分配以实现绑定链路上的分组流的均匀分布。 绑定端口可能具有不同的带宽，在这种情况下，流量按比例分配。

公开(公告)号：EP0910195A2

公开(公告)日：1999-04-21

申请号：EP98307556.5

申请日：1998-09-17

Applicant: Compaq Computer Corporation

Inventor： Witkowski, Michael L. ,  Mayer, Dale J. ,  Walker, William J. ,  Roller, Kirk D. ,  Hareski, Patricia E. ,  Kotzur, Gary B.

IPC: H04L12/46 ,  H04L29/00

CPC classification number: H04L12/467 ,  H04L49/201 ,  H04L49/205 ,  H04L49/254 ,  H04L49/351 ,  H04L49/354 ,  H04L69/14

Abstract: A network communication device including port control circuitry for controlling packet flow between the ports of the device, where the port control circuitry includes a port manager that directs packets between the ports and port bonding circuitry that bonds two or more ofthe ports into a bonded port set. For each packet to be sent via the bonded port set, the port bonding circuitry selects one of the bonded ports for transmitting the packet. More than one bonded port set may be defined in a given communication device, and each bonded port set may include from two ports up to all the ports of the device, as long as each port is included in only one bonded port set. One or more port bonding registers are provided to identify which ofthe plurality ofports are bonded in each bonded port set. In one embodiment, the bonded ports are selected on a packet by packet basis so as to achieve a relatively even distribution of packets sent by each bonded port. In an alternative embodiment bonded ports are assigned to packet source identifiers so as to achieve a relatively even distribution of source identifiers among the bonded ports. If bonded ports are assigned to particular source identifiers, then the traffic is preferably monitored and the assignments are periodically adjusted to achieve even distribution of packet flow on the bonded link. The bonded ports may have different bandwidths, in which case traffic is distributed on a proportionate basis.

Abstract translation: 一种网络通信设备，包括用于控制设备端口之间的分组流的端口控制电路，其中端口控制电路包括端口管理器，该端口管理器在端口之间引导分组，并且端口连接电路将两个或多个端口绑定到绑定端口组 。 对于要通过绑定端口组发送的每个分组，端口绑定电路选择用于发送分组的绑定端口之一。 可以在给定的通信设备中定义多个绑定端口组，并且每个绑定端口组可以包括直到设备的所有端口的两个端口，只要每个端口仅包括在一个绑定端口组中。 提供一个或多个端口绑定寄存器以识别在每个绑定端口组中的多个端口中的哪一个被绑定。 在一个实施例中，按照分组的方式选择绑定端口，以便实现每个绑定端口发送的分组的相对均匀的分布。 在替代实施例中，绑定端口被分配给分组源标识符，以便在绑定端口之间实现源标识符的相对均匀的分布。 如果绑定端口被分配给特定的源标识符，则优选地监视流量并且周期性地调整分配以实现绑定链路上的分组流的均匀分布。 绑定端口可以具有不同的带宽，在这种情况下，业务量按比例分配。

公开(公告)号：EP0854613A2

公开(公告)日：1998-07-22

申请号：EP97310663.6

申请日：1997-12-30

Applicant: Compaq Computer Corporation

Inventor： Witkowski, Michael L. ,  Chandler, Gregory T. ,  Khan, Mohammed A. ,  Kotzur, Gary B. ,  Mayer, Dale J. ,  Walker, William J.

IPC: H04L12/44 ,  H04L12/40 ,  H04L12/46 ,  H04L12/56

CPC classification number: H04L49/351 ,  H04L49/205 ,  H04L49/354 ,  Y10S370/911

Abstract: A network switch including a plurality of first network ports, a plurality of second network ports, a first bus, a second bus and a bridge interface coupled between the first and second buses. The first ports receive and transmit network data according to a first network protocol and the second ports receive and transmit network data according to a second network protocol. The first and second buses operate according to different bus standards. The bridge interface enables data transfer between the first and second buses and thus between the networks operating at different protocols. The switch includes a switch manager that controls the flow of network data and a processor for performing supervisory and control functions. The bridge interface includes receive buffers and transmit buffers assigned to respective ports. During packet data transfer operations across the first bus, the bridge interface emulates a first network port. During packet data transfer operations across the second bus, the bridge interface primarily acts as a slave to the second network ports by storing control lists for execution by the second network ports. This processor is relieved of performing necessary overhead functions associated with the second bus and is thus freed to perform other important switch functions.

Abstract translation: 网络交换机包括第一网络端口复数，第二网络端口复数，第一总线，第二总线以及耦合在第一和第二总线之间的桥接口。 所述第一端口接收和发送的网络数据gemäß到第一网络协议和所述第二端口接收和发送的网络数据gemäß到第二网络协议。 所述第一和第二总线操作gemäß到不同的总线标准。 网桥接口启用第一和第二总线之间，因而在不同的协议操作的网络之间的数据传送。 该开关包括一个交换机管理器那样控制网络的数据流和用于执行监视和控制功能的处理器。 网桥接口包括接收缓冲器和发送分配给respectivement端口缓冲器。 期间在所述第一总线分组数据传输操作中，桥接口模仿第一网络端口。期间通过第二总线分组数据传送操作中，网桥接口主要由存储控制列表执行充当从属到第二网络端口 第二个网络端口。 该处理器被解除执行与所述第二总线相关联的必要的开销功能的，因此是自由地执行其它重要功能进行切换。

公开(公告)号：EP0854611A2

公开(公告)日：1998-07-22

申请号：EP97310656.0

申请日：1997-12-30

Applicant: Compaq Computer Corporation

Inventor： Walker, William J. ,  Kotzur, Gary B. ,  Hareski, Patricia E. ,  Mayer, Dale J. ,  Witkowski, Michael L.

IPC: H04L12/44 ,  H04L12/40 ,  H04L12/56

CPC classification number: H04L49/351 ,  H04L49/201 ,  H04L49/205 ,  H04L49/254 ,  Y10S370/911

Abstract: A network switch including one or more network ports for receiving and transmitting data, where each port includes a network interface, a data bus interface and a processor port interface. a data bus coupled to the data bus interface of each of the ports, a processor bus coupled to a processor and to the processor port interface of each of the ports, and a memory bus coupled to a memory. The network switch further includes a switch manager coupled to the data bus, the processor bus and the memory bus for controlling data flow between the ports and said memory and for enabling the processor access to the ports and the memory. In this manner, the processor has direct and relatively independent access to the network ports for performing overhead functions, such as monitoring, determining status and configuration without consuming valuable bandwidth of the data bus.

Abstract translation: 一种网络交换机，包括用于接收和发送数据的一个或多个网络端口，其中每个端口包括网络接口，数据总线接口和处理器端口接口。 耦合到每个端口的数据总线接口的数据总线，耦合到每个端口的处理器和处理器端口接口的处理器总线，以及耦合到存储器的存储器总线。 网络交换机还包括耦合到数据总线的开关管理器，处理器总线和存储器总线，用于控制端口和所述存储器之间的数据流，并使处理器能够访问端口和存储器。 以这种方式，处理器具有对网络端口的直接和相对独立的访问，用于执行开销功能，例如监视，确定状态和配置，而不消耗数据总线的有价值的带宽。