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1.发明公开Method and apparatus for distributing interrupts in a scalable symmetric multiprocessor system without changing the bus width or bus protocol 失效改变的方法和装置，用于中断在一个可扩展的对称多处理器系统分布，而不总线宽度或总线协议
公开(公告)号：EP0827085A2
公开(公告)日：1998-03-04
申请号：EP97306157.5
申请日：1997-08-13
Applicant: Compaq Computer Corporation
Inventor： Mayer, Dale J. , Olarig, Sompong P. , Whiteman, William F. , Heinrich, David F.
IPC: G06F13/24
CPC classification number: G06F13/24
Abstract: A method for supporting multiple distributed interrupt controllers, designated as bus agents, in a symmetric multiprocessing system, includes the steps of assigning a unique identification number to each bus agent, receiving bus requests from the bus agents over four data lines in groups of four, and granting bus ownership to a selected one of the requesting bus agents. Similarly, a computer system that supports multiple distributed interrupt controllers, designated as bus agents, in a symmetric multiprocessing system, includes structure for assigning a unique identification number to each bus agent, four data lines for receiving bus requests from the bus agents in groups of four, and structure for granting bus ownership to a selected one of the requesting bus agents.
Abstract translation: 一种用于支持多个分布式中断控制器，被指定为总线代理，在一个对称多处理系统的方法，包括：分配唯一的识别号码给每个总线代理，在四个一组接收通过四条数据线从总线代理的总线请求的步骤， 并授予总线所有权请求总线代理的选择之一。 类似地，计算机系统都支持多个分布式中断控制器，被指定为总线代理，在一个对称多处理系统，包括：用于分配一个唯一的标识号给每个总线代理的结构，用于接收在一组从所述总线代理的总线请求四条数据线 4，和结构授予总线所有权给请求总线代理中选择的一个。
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2.发明授权Method and apparatus for distributing interrupts in a scalable symmetric multiprocessor system without changing the bus width or bus protocol 失效改变的方法和装置，用于中断在一个可扩展的对称多处理器系统分布，而不总线宽度或总线协议
公开(公告)号：EP0827085B1
公开(公告)日：2006-03-29
申请号：EP97306157.5
申请日：1997-08-13
Applicant: Compaq Computer Corporation
Inventor： Mayer, Dale J. , Olarig, Sompong P. , Whiteman, William F. , Heinrich, David F.
IPC: G06F13/24
CPC classification number: G06F13/24
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公开(公告)号：EP0945777A3
公开(公告)日：2000-09-06
申请号：EP99302082.5
申请日：1999-03-18
Applicant: Compaq Computer Corporation
Inventor： Heinrich, David F. , Le, Harry Q. , Waldorf, Richard O. , Angelo, Michael F.
CPC classification number: G06F13/4027 , G06F21/31 , G06F21/82
Abstract: A computer password security method employing a south bridge circuitry where the user password is compared to a secured password stored in secured memory which is directly accessible to the south bridge circuitry, removing any threat of data bus and/or unprotected memory snooping.
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Patent Agency Ranking4.发明公开Computer architecture with password-checking bus bridge 审中-公开肯尼多乐斯（Kennwortes）的Rechnerarchitektur mit einerBusbrückezurPrüfung
公开(公告)号：EP0945777A2
公开(公告)日：1999-09-29
申请号：EP99302082.5
申请日：1999-03-18
Applicant: Compaq Computer Corporation
Inventor： Heinrich, David F. , Le, Harry Q. , Waldorf, Richard O. , Angelo, Michael F.
IPC: G06F1/00
CPC classification number: G06F13/4027 , G06F21/31 , G06F21/82
Abstract: A computer password security method employing a south bridge circuitry where the user password is compared to a secured password stored in secured memory which is directly accessible to the south bridge circuitry, removing any threat of data bus and/or unprotected memory snooping.
Abstract translation: 一种使用南桥电路的计算机密码安全方法，其中将用户密码与存储在安全存储器中的安全密码进行比较，该安全密码可直接访问南桥电路，消除数据总线和/或不受保护的存储器窥探的任何威胁。
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5.发明公开Circuit for reassigning the power-on processor in a multiprocessing system 失效einch Mehrprozessorensystem的Schaltung zum Wiederzuweisen des Einschaltsprozessors
公开(公告)号：EP0720094A2
公开(公告)日：1996-07-03
申请号：EP95309547.8
申请日：1995-12-29
Applicant: Compaq Computer Corporation
Inventor： Goodrum, Alan A. , Kotzur, Gary B. , Lantz, Kurt C. , Heinrich, David F. , Wilson, Jeffrey R.
CPC classification number: G06F15/177 , G06F1/26 , G06F11/1417
Abstract: A hot spare boot circuit that automatically switches from a non-operational CPU to an operational CPU for powering up the computer system. In the multiprocessor computer system, a first CPU is designated to perform power on operations. If the first CPU fails, which is determined when a dead man counter in the hot spare boot circuit times out, the hot spare circuit ensures that the first CPU is in a disabled state. Next, the hot spare boot circuit identifies an operational second CPU, reinitializing certain ID information as necessary such that the second CPU can properly perform power on operations. The hot spare boot then awakens the second CPU, using a startup interprocessor interrupt in one embodiment, or simply negating the hard reset of the second CPU in a second embodiment. The second CPU then proceeds to perform the power on functions.
Abstract translation: 一个热备用引导电路，可自动从非操作CPU切换到运行CPU，以便为计算机系统供电。 在多处理器计算机系统中，指定第一CPU执行上电操作。 如果第一个CPU出现故障，当热备用引导电路中的死亡计数器超时时，该热备用电路确保第一个CPU处于禁用状态。 接下来，热备用引导电路识别操作的第二CPU，根据需要重新初始化某些ID信息，使得第二CPU可以正常地执行上电操作。 在第二实施例中，热备用引导然后唤醒第二CPU，在一个实施例中使用启动处理器中断，或简单地否定第二CPU的硬复位。 然后第二个CPU继续执行上电功能。
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6.发明授权Circuit for reassigning the power-on processor in a multiprocessing system 失效电路的重新分配在多处理器系统中的Einschaltsprozessors
公开(公告)号：EP0720094B1
公开(公告)日：2002-07-24
申请号：EP95309547.8
申请日：1995-12-29
Applicant: Compaq Computer Corporation
Inventor： Goodrum, Alan A. , Kotzur, Gary B. , Lantz, Kurt C. , Heinrich, David F. , Wilson, Jeffrey R.
CPC classification number: G06F15/177 , G06F1/26 , G06F11/1417
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7.发明公开Method and apparatus for distributing interrupts in a scalable symmetric multiprocessor system without changing the bus width or bus protocol 失效改变的方法和装置，用于中断在一个可扩展的对称多处理器系统分布，而不总线宽度或总线协议
公开(公告)号：EP0827085A3
公开(公告)日：1999-02-03
申请号：EP97306157.5
申请日：1997-08-13
Applicant: Compaq Computer Corporation
Inventor： Mayer, Dale J. , Olarig, Sompong P. , Whiteman, William F. , Heinrich, David F.
IPC: G06F13/24
CPC classification number: G06F13/24
Abstract: A method for supporting multiple distributed interrupt controllers, designated as bus agents, in a symmetric multiprocessing system, includes the steps of assigning a unique identification number to each bus agent, receiving bus requests from the bus agents over four data lines in groups of four, and granting bus ownership to a selected one of the requesting bus agents. Similarly, a computer system that supports multiple distributed interrupt controllers, designated as bus agents, in a symmetric multiprocessing system, includes structure for assigning a unique identification number to each bus agent, four data lines for receiving bus requests from the bus agents in groups of four, and structure for granting bus ownership to a selected one of the requesting bus agents.
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8.发明公开Circuit for reassigning the power-on processor in a multiprocessing system 失效电路的重新分配在多处理器系统中的Einschaltsprozessors
公开(公告)号：EP0720094A3
公开(公告)日：1997-04-23
申请号：EP95309547.8
申请日：1995-12-29
Applicant: Compaq Computer Corporation
Inventor： Goodrum, Alan A. , Kotzur, Gary B. , Lantz, Kurt C. , Heinrich, David F. , Wilson, Jeffrey R.
CPC classification number: G06F15/177 , G06F1/26 , G06F11/1417
Abstract: A hot spare boot circuit that automatically switches from a non-operational CPU to an operational CPU for powering up the computer system. In the multiprocessor computer system, a first CPU is designated to perform power on operations. If the first CPU fails, which is determined when a dead man counter in the hot spare boot circuit times out, the hot spare circuit ensures that the first CPU is in a disabled state. Next, the hot spare boot circuit identifies an operational second CPU, reinitializing certain ID information as necessary such that the second CPU can properly perform power on operations. The hot spare boot then awakens the second CPU, using a startup interprocessor interrupt in one embodiment, or simply negating the hard reset of the second CPU in a second embodiment. The second CPU then proceeds to perform the power on functions.
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