公开(公告)号：US11848324B2

公开(公告)日：2023-12-19

申请号：US17483104

申请日：2021-09-23

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ephrem G. Gebreselasie ,  Steven M. Shank ,  Alain F. Loiseau ,  Robert J. Gauthier, Jr. ,  Michel J. Abou-Khalil ,  Ahmed Y. Ginawi

IPC: H01L27/06 ,  H01L23/525 ,  H01L21/8234

CPC classification number: H01L27/0629 ,  H01L21/823481 ,  H01L23/5256

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an eFuse and gate structure on a triple-well and methods of manufacture. The structure includes: a substrate comprising a bounded region; a gate structure formed within the bounded region; and an eFuse formed within the bounded region and electrically connected to the gate structure.

公开(公告)号：US11349304B2

公开(公告)日：2022-05-31

申请号：US17082182

申请日：2020-10-28

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Alain F. Loiseau ,  Robert J. Gauthier, Jr. ,  Souvick Mitra ,  You Li ,  Meng Miao ,  Wei Liang

IPC: H02H9/04 ,  H01L27/02

Abstract: Embodiments of the disclosure provide a circuit structure and method to control electrostatic discharge (ESD) events in a resistor-capacitor (RC) circuit. Circuit structures according to the disclosure may include a trigger transistor coupled in parallel with the RC circuit, and a gate terminal coupled to part of the RC circuit. A mirror transistor coupled in parallel with the RC circuit transmits a current that is less than a current through the trigger transistor. A snapback device has a gate terminal coupled to a source or drain of the mirror transistor, and a pair of anode/cathode terminals coupled in parallel with the RC circuit. A current at the gate terminal of the snapback device, derived from current in the mirror transistor, controls an anode/cathode current flow in the snapback device.

公开(公告)号：US11335674B2

公开(公告)日：2022-05-17

申请号：US16455071

申请日：2019-06-27

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Souvick Mitra ,  Robert J. Gauthier, Jr. ,  Alain F. Loiseau ,  You Li ,  Tsung-Che Tsai

IPC: H01L27/02

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to diode triggered Silicon controlled rectifiers and methods of manufacture. The structure includes a diode string comprising a first type of diodes and a second type of diode in bulk technology in series with the diode string of the first type of diodes.

公开(公告)号：US11171132B2

公开(公告)日：2021-11-09

申请号：US16592013

申请日：2019-10-03

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Souvick Mitra ,  Alain F. Loiseau ,  Robert J. Gauthier, Jr. ,  You Li ,  Tsung-Che Tsai

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/747 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bi-directional silicon controlled rectifiers (SCRs) and methods of manufacture. The structure includes: a plurality of diffusion regions; a plurality of p-type (P+) wells adjacent to the diffusion regions, wherein the P+ wells are directly connected; and a plurality of n-type (N+) wells adjacent to the P+ wells.

公开(公告)号：US20250006650A1

公开(公告)日：2025-01-02

申请号：US18341893

申请日：2023-06-27

Applicant: GlobalFoundries U.S. Inc.

Inventor： Alain F. Loiseau ,  Romain H.A. Feuillette ,  Mujahid Muhammad ,  Peter T. Coutu

IPC: H01L23/544 ,  G01R31/28

Abstract: An integrated circuit (IC) includes a plurality of metal layers, and a machine-readable code in a selected metal layer of the plurality of metal layers. A wafer includes a plurality of the ICs. An IC wafer testing system includes a scanner configured to read the machine-readable code in the metal layer of the IC in the wafer, and a tester configured to perform testing on the IC in the wafer based on testing information obtained from storage based on the machine-readable code. A method may include forming the IC including a plurality of metal layers and forming a selected metal layer of the IC including the machine-readable code in metal in the selected metal layer. The method may further include testing the IC. The machine-readable code reduces the complexity and time needed to setup and test an IC in a wafer.

公开(公告)号：US20240074167A1

公开(公告)日：2024-02-29

申请号：US17895156

申请日：2022-08-25

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anindya Nath ,  Ephrem G. Gebreselasie ,  Rajendran Krishnasamy ,  Alain F. Loiseau

IPC: H01L27/112 ,  H01L23/525 ,  H01L29/735

CPC classification number: H01L27/11206 ,  H01L23/5256 ,  H01L29/735

Abstract: Embodiments of the disclosure provide a circuit structure including an electrically programmable fuse (efuse) and lateral bipolar transistor. A structure of the disclosure includes a lateral bipolar transistor within a semiconductor layer and over a substrate. An insulator layer is over a portion of the semiconductor layer. An efuse structure is within a polycrystalline semiconductor layer and over the insulator layer. The efuse structure is over a current path through the lateral bipolar transistor.

公开(公告)号：US20230420448A1

公开(公告)日：2023-12-28

申请号：US17808364

申请日：2022-06-23

Applicant: GlobalFoundries U.S. Inc.

Inventor： Souvick Mitra ,  Alain F. Loiseau ,  Robert J. Gauthier, JR. ,  Meng Miao ,  Anindya Nath ,  Wei Liang

IPC: H01L27/02 ,  H01L29/74

CPC classification number: H01L27/0262 ,  H01L29/7436

Abstract: A structure includes trigger control circuitry for an SCR including: a first transistor having two P-type semiconductor terminals connected to an Nwell and a Pwell of the SCR; a second transistor having two N-type semiconductor terminals connected to the Pwell and ground; and, optionally, an additional transistor having two P-type semiconductor terminals connected to the Nwell and ground. Control terminals of the transistors receive the same control signal (e.g., RST from a power-on-reset). When a circuit connected to the SCR for ESD protection is powered on, ESD risk is limited so RST switches to high. Thus, the first transistor and optional additional transistor turn off and the second transistor turns on, reducing leakage. When the circuit is powered down, the ESD risk increases so RST switches to low. Thus, the first transistor and optional additional transistor turn on and the second transistor turns off, lowering the trigger voltage and current.

公开(公告)号：US20230402447A1

公开(公告)日：2023-12-14

申请号：US17806797

申请日：2022-06-14

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anindya Nath ,  Alain F. Loiseau ,  Rajendran Krishnasamy ,  Souvick Mitra

IPC: H01L27/02 ,  H01L29/87

CPC classification number: H01L27/0248 ,  H01L29/87

Abstract: Disclosed are a structure and method. The structure includes a substrate having monocrystalline lower and upper portions and a high resistance portion (e.g., a trap-rich amorphous portion) between the lower and upper portions. An isolation region extends through the upper portion, is above the high resistance portion, and is positioned laterally adjacent to a device section of the upper portion also above the high resistance portion. One or more devices (e.g., a diode, multiple diodes, a diode string, multiple diode strings, etc.) are on the trench isolation region, on the device section, and/or within the device section. The device(s) are separated from the lower portion by the high resistance portion and, potentially, by the isolation region or the device section. Such device(s) can be employed for electrostatic discharge (ESD) protection on RFIC chips and can sustain a larger RF voltage, provide area savings, reduce parasitic capacitance, improve harmonics, etc.

公开(公告)号：US11804481B2

公开(公告)日：2023-10-31

申请号：US17185243

申请日：2021-02-25

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Robert J. Gauthier, Jr. ,  Meng Miao ,  Alain F. Loiseau ,  Souvick Mitra ,  You Li ,  Wei Liang

IPC: H01L27/02 ,  H01L21/84 ,  H01L21/8222 ,  H01L27/12

CPC classification number: H01L27/0259 ,  H01L21/8222 ,  H01L21/84 ,  H01L27/0288 ,  H01L27/1207

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) devices and methods of manufacture. The structure (ESD device) includes: a bipolar transistor comprising a collector region, an emitter region and a base region; and a lateral ballasting resistance comprising semiconductor material adjacent to the collector region.

公开(公告)号：US11769767B2

公开(公告)日：2023-09-26

申请号：US17704422

申请日：2022-03-25

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Souvick Mitra ,  Robert J. Gauthier, Jr. ,  Alain F. Loiseau ,  You Li ,  Tsung-Che Tsai

IPC: H01L27/02

CPC classification number: H01L27/0255 ,  H01L27/0262

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to diode triggered Silicon controlled rectifiers and methods of manufacture. The structure includes a diode string comprising a first type of diodes and a second type of diode in bulk technology in series with the diode string of the first type of diodes.