公开(公告)号：US12107083B2

公开(公告)日：2024-10-01

申请号：US18462779

申请日：2023-09-07

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Robert J. Gauthier, Jr. ,  Meng Miao ,  Alain F. Loiseau ,  Souvick Mitra ,  You Li ,  Wei Liang

IPC: H01L27/02 ,  H01L21/8222 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L27/0259 ,  H01L21/8222 ,  H01L21/84 ,  H01L27/0288 ,  H01L27/1207

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) devices and methods of manufacture. The structure (ESD device) includes: a bipolar transistor comprising a collector region, an emitter region and a base region; and a lateral ballasting resistance comprising semiconductor material adjacent to the collector region.

公开(公告)号：US12051690B2

公开(公告)日：2024-07-30

申请号：US17523956

申请日：2021-11-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Sagar Premnath Karalkar ,  Prantik Mahajan ,  Jie Zeng ,  Ajay Ajay ,  Milova Paul ,  Souvick Mitra

IPC: H01L27/02

CPC classification number: H01L27/0262

Abstract: Disclosed is a semiconductor structure including a semiconductor substrate (e.g., a P-substrate) and a symmetric BDSCR. The BDSCR includes, within the substrate, a first well (e.g., a low-doped deep Nwell) and, within the first well, symmetric side sections and a middle section positioned laterally between the side sections. Each side section includes: second and third wells (e.g., Pwells), where the third well is shallower than and has a higher conductivity level than the second well. Each middle section includes multiple floating wells including: two fourth wells (e.g., Nwells), which have a higher conductivity level than the first well, and a fifth well (e.g., another Pwell), which is positioned laterally between and shallower than the fourth wells. By incorporating the floating wells into the middle section, high current tolerance is improved.

公开(公告)号：US20240234409A1

公开(公告)日：2024-07-11

申请号：US18152420

申请日：2023-01-10

Applicant: GlobalFoundries U.S. Inc.

Inventor： Sagar Premnath Karalkar ,  Ephrem G. Gebreselasie ,  Rajendran Krishnasamy ,  Robert J. Gauthier, JR. ,  Souvick Mitra

IPC: H01L27/02

CPC classification number: H01L27/0262

Abstract: The disclosure provides a structure including an n-type well over an n-type deep well and between a pair of p-type wells for electrostatic discharge (ESD) protection. The structure may include a p-type deep well over a substrate, a first n-type well over the p-type deep well, and a pair of p-type wells over the p-type deep well. The pair of p-type wells are each adjacent opposite horizontal ends of the n-type well. A pair of second n-type wells are over the p-type deep well and adjacent one of the pair of p-type wells. Each p-type well is horizontally between the first n-type well and one of the second n-type wells.

公开(公告)号：US20240170531A1

公开(公告)日：2024-05-23

申请号：US18056289

申请日：2022-11-17

Applicant: GlobalFoundries U.S. Inc.

Inventor： Sagar Premnath Karalkar ,  Jie Zeng ,  Souvick Mitra

IPC: H01L29/06 ,  H01L27/02

CPC classification number: H01L29/0623 ,  H01L27/0248

Abstract: The disclosure provides a structure with a buried doped region, and methods to form the same. A structure may include a semiconductor substrate including a first well. A first terminal includes a first doped region in the first well. A second terminal includes a second doped region in the first well. The first well horizontally separates the first doped region from the second doped region. A first buried doped region is in the first well. The first buried doped region overlaps with, and is underneath, the first doped region. The first well vertically separates the first doped region from the first buried doped region.

公开(公告)号：US20230420551A1

公开(公告)日：2023-12-28

申请号：US17849867

申请日：2022-06-27

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh Mani Pandey ,  Souvick Mitra ,  Anindya Nath

IPC: H01L29/745 ,  H01L29/66

CPC classification number: H01L29/7455 ,  H01L29/66363

Abstract: Structures for a silicon-controlled rectifier and methods of forming a structure for a silicon-controlled rectifier. The structure comprises a semiconductor substrate, a dielectric layer on the semiconductor substrate, and a first well and a second well in the semiconductor substrate beneath the dielectric layer. The first well has a first conductivity type, the second well has a second conductivity type opposite to the first conductivity type, and the second well adjoins the first well along a p-n junction. The structure further comprises a first terminal and a second terminal above the dielectric layer, a first connection extending through the dielectric layer from the first terminal to the first well, and a second connection extending through the dielectric layer from the second terminal to the second well.

公开(公告)号：US11791626B2

公开(公告)日：2023-10-17

申请号：US17490371

申请日：2021-09-30

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： You Li ,  Alain F. Loiseau ,  Souvick Mitra ,  Tsung-Che Tsai ,  Mickey Yu ,  Robert J. Gauthier, Jr.

IPC: H02H9/04 ,  H01L27/02 ,  H02H1/00 ,  H01L23/60

CPC classification number: H02H9/046 ,  H01L23/60 ,  H01L27/0255 ,  H01L27/0262 ,  H01L27/0288 ,  H01L27/0292 ,  H02H1/0007

Abstract: A circuit structure includes: a network of clamps; sense elements in series with the clamps and configured to sense a turn-on of at least one clamp of the network of clamps; and feedback elements connected to the clamps to facilitate triggering of remaining clamps of the network of clamps.

公开(公告)号：US20220131369A1

公开(公告)日：2022-04-28

申请号：US17082182

申请日：2020-10-28

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Alain F. Loiseau ,  Robert J. Gauthier, JR. ,  Souvick Mitra ,  You Li ,  Meng Miao ,  Wei Liang

IPC: H02H9/04 ,  H01L27/02

Abstract: Embodiments of the disclosure provide a circuit structure and method to control electrostatic discharge (ESD) events in a resistor-capacitor (RC) circuit. Circuit structures according to the disclosure may include a trigger transistor coupled in parallel with the RC circuit, and a gate terminal coupled to part of the RC circuit. A mirror transistor coupled in parallel with the RC circuit transmits a current that is less than a current through the trigger transistor. A snapback device has a gate terminal coupled to a source or drain of the mirror transistor, and a pair of anode/cathode terminals coupled in parallel with the RC circuit. A current at the gate terminal of the snapback device, derived from current in the mirror transistor, controls an anode/cathode current flow in the snapback device.

公开(公告)号：US20220037309A1

公开(公告)日：2022-02-03

申请号：US16983071

申请日：2020-08-03

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Robert J. Gauthier, JR. ,  Alain F. Loiseau ,  Souvick Mitra ,  Tsung-Che Tsai ,  Meng Miao ,  You Li

IPC: H01L27/02

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including a doped well in a semiconductor substrate, in addition to a base region, emitter region, and collector region in the doped well. An insulative material is within the doped well, with a first end horizontally adjacent the collector region and a second end opposite the first end. A doped semiconductor region is within the doped well adjacent the second end of the insulative material. The doped semiconductor region is positioned to define an avalanche junction between the collector region and the doped semiconductor region across the doped well.

公开(公告)号：US20250031457A1

公开(公告)日：2025-01-23

申请号：US18223780

申请日：2023-07-19

Applicant: GlobalFoundries U.S. Inc.

Inventor： Sagar Premnath Karalkar ,  . Ajay ,  Souvick Mitra ,  Kyong Jin Hwang

IPC: H01L27/02

Abstract: Structures for an electrostatic discharge protection device and methods of forming same. The structure comprises a semiconductor substrate including a well, a field-effect transistor including a gate, a source having a doped region in the well, and a drain, and a silicon-controlled rectifier including a doped region in the well.

公开(公告)号：US12205943B2

公开(公告)日：2025-01-21

申请号：US17890725

申请日：2022-08-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anindya Nath ,  Alain F. Loiseau ,  Souvick Mitra ,  Rajendran Krishnasamy

IPC: H01L27/02 ,  H01L29/73 ,  H01L29/735 ,  H01L29/739

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure with a diode over a lateral bipolar transistor. A structure according to the disclosure may include a lateral bipolar transistor within a monocrystalline semiconductor over a substrate. An insulator layer is over a portion of the monocrystalline semiconductor. A diode is within a polycrystalline semiconductor on the insulator layer. A cathode of the diode is coupled to a first well within the monocrystalline semiconductor. The first well defines one of an emitter terminal and a collector terminal of the lateral bipolar transistor.