公开(公告)号：US20230395714A1

公开(公告)日：2023-12-07

申请号：US17831496

申请日：2022-06-03

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anindya Nath ,  Alain Loiseau ,  Rajendran Krishnasamy

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/7835 ,  H01L21/823892 ,  H01L29/66659

Abstract: Device structures with an isolation well and methods of forming a device structure with an isolation well. The structure comprises a first well of a first conductivity type in a semiconductor substrate, and a second well of a second conductivity type in the semiconductor substrate. The second conductivity type is opposite to the first conductivity type. The first well includes a plurality of segments, and the second well is positioned in a vertical direction between the segments of the first well and a top surface of the semiconductor substrate.

公开(公告)号：US20230317776A1

公开(公告)日：2023-10-05

申请号：US17708561

申请日：2022-03-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： Michel Abou-Khalil ,  Steven M. Shank ,  Aaron Vallett ,  Sarah McTaggart ,  Rajendran Krishnasamy

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/0649 ,  H01L29/4236 ,  H01L29/1087

Abstract: Semiconductor structures including electrical isolation and methods of forming a semiconductor structure including electrical isolation. The structure includes a semiconductor substrate having a first surface, a recess in the first surface, and a second surface inside the first recess. The structure further includes a shallow trench isolation region extending from the first surface into the semiconductor substrate. The shallow trench isolation region is positioned to surround an active device region including the recess. A field-effect transistor includes a gate electrode positioned on a portion of the second surface.

公开(公告)号：US20230268394A1

公开(公告)日：2023-08-24

申请号：US17679166

申请日：2022-02-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Sarah A. McTaggart ,  Rajendran Krishnasamy ,  Qizhi Liu

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/732 ,  H01L29/737 ,  H01L21/265

CPC classification number: H01L29/0817 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7371 ,  H01L21/26586

Abstract: Disclosed are a structure including a transistor and a method of forming the structure. The transistor includes an emitter region with first and second emitter portions. The first emitter portion extends through a dielectric layer. The second emitter portion is on the first emitter portion and the top of the dielectric layer. An additional dielectric layer covers the top of the second emitter portion. The second emitter portion and the dielectric and additional dielectric layers are wider than the first emitter portion. At least a section of the second emitter portion is narrower than the dielectric and additional dielectric layers, thereby creating cavities positioned vertically between edge portions of the dielectric and additional dielectric layers and positioned laterally adjacent to the second emitter portion. The cavities are filled with dielectric material or dielectric material blocks the side openings to the cavities creating pockets of air, of gas or under vacuum.

公开(公告)号：US12293994B2

公开(公告)日：2025-05-06

申请号：US17955225

申请日：2022-09-28

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vvss Satyasuresh Choppalli ,  Anupam Dutta ,  Rajendran Krishnasamy ,  Robert Gauthier, Jr. ,  Xiang Xiang Lu ,  Anindya Nath

IPC: H01L25/07 ,  H01L21/77 ,  H01L23/14 ,  H01L23/522

Abstract: Structures including multiple semiconductor devices and methods of forming same. The structure comprises a first device structure including a first well and a second well in a semiconductor substrate, a second device structure including a doped region in the semiconductor substrate, and a first high-resistivity region in the semiconductor substrate. The first well has a first conductivity type, the second well has a second conductivity type opposite to the first conductivity type, and the first well adjoins the second well to define a p-n junction. The doped region of the second device structure has the first conductivity type or the second conductivity type. The high-resistivity region has a higher electrical resistivity than the semiconductor substrate, and the high-resistivity region is positioned between the first device structure and the second device structure.

公开(公告)号：US12237407B2

公开(公告)日：2025-02-25

申请号：US17978633

申请日：2022-11-01

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anupam Dutta ,  Rajendran Krishnasamy ,  Vvss Satyasuresh Choppalli ,  Vibhor Jain ,  Robert J. Gauthier, Jr.

IPC: H01L29/737

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich region and methods of manufacture. The structure includes: a heterojunction bipolar transistor comprising a collector region, a base region and an emitter region; and at least one non-single-crystal semiconductor region in the collector region of the heterojunction bipolar transistor.

公开(公告)号：US20240234533A1

公开(公告)日：2024-07-11

申请号：US18152710

申请日：2023-01-10

Applicant: GlobalFoundries U.S. Inc.

Inventor： Santosh Sharma ,  Shesh Mani Pandey ,  Rajendran Krishnasamy

IPC: H01L29/47 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/475 ,  H01L29/401 ,  H01L29/66462 ,  H01L29/7786

Abstract: Disclosed is a structure including a substrate and a transistor on the substrate. The transistor includes a barrier layer above the substrate and a multi-gate structure on the barrier layer. The multi-gate structure includes a primary gate and a secondary gate. The secondary gate has opposing sidewalls, opposing end walls and a top surface. The primary gate includes essentially vertically-oriented first portions on the barrier layer positioned laterally adjacent to opposing sidewalls, respectively, of the secondary gate. Optionally, the primary gate also includes an essentially horizontally-oriented second portion on the top surface of the secondary gate and/or essentially vertically-oriented third portions on the opposing end walls, respectively. The secondary gate can be a floating gate. Also disclosed is a method of forming the structure.

公开(公告)号：US20240234409A1

公开(公告)日：2024-07-11

申请号：US18152420

申请日：2023-01-10

Applicant: GlobalFoundries U.S. Inc.

Inventor： Sagar Premnath Karalkar ,  Ephrem G. Gebreselasie ,  Rajendran Krishnasamy ,  Robert J. Gauthier, JR. ,  Souvick Mitra

IPC: H01L27/02

CPC classification number: H01L27/0262

Abstract: The disclosure provides a structure including an n-type well over an n-type deep well and between a pair of p-type wells for electrostatic discharge (ESD) protection. The structure may include a p-type deep well over a substrate, a first n-type well over the p-type deep well, and a pair of p-type wells over the p-type deep well. The pair of p-type wells are each adjacent opposite horizontal ends of the n-type well. A pair of second n-type wells are over the p-type deep well and adjacent one of the pair of p-type wells. Each p-type well is horizontally between the first n-type well and one of the second n-type wells.

公开(公告)号：US11972999B2

公开(公告)日：2024-04-30

申请号：US17643023

申请日：2021-12-07

Applicant: GlobalFoundries U.S. Inc.

Inventor： Mark D. Levy ,  Rajendran Krishnasamy ,  Michael J. Zierak ,  Siva P. Adusumilli

IPC: H01L23/367 ,  H01L23/373 ,  H01L29/417 ,  H01L29/732

CPC classification number: H01L23/367 ,  H01L23/3736 ,  H01L29/41708 ,  H01L29/7325

Abstract: A structure includes an electrical device, and an active contact landed on a portion of the electrical device. The active contact includes a first body of a first material. A thermal dissipation pillar is adjacent the active contact and unlanded on but over the portion of the electrical device. The thermal dissipation pillar includes a second body of a second material having a higher thermal conductivity than the first material. The thermal dissipation pillar may be in thermal communication with a wire in a dielectric layer over the active contact and the thermal dissipation pillar. The electrical device can be any integrated circuit device that generates heat.

公开(公告)号：US20240105683A1

公开(公告)日：2024-03-28

申请号：US17955225

申请日：2022-09-28

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vvss Satyasuresh Choppalli ,  Anupam Dutta ,  Rajendran Krishnasamy ,  Robert Gauthier, JR. ,  Xiang Xiang Lu ,  Anindya Nath

IPC: H01L25/07 ,  H01L21/77 ,  H01L23/14 ,  H01L23/522

CPC classification number: H01L25/072 ,  H01L21/77 ,  H01L23/147 ,  H01L23/5228

Abstract: Structures including multiple semiconductor devices and methods of forming same. The structure comprises a first device structure including a first well and a second well in a semiconductor substrate, a second device structure including a doped region in the semiconductor substrate, and a first high-resistivity region in the semiconductor substrate. The first well has a first conductivity type, the second well has a second conductivity type opposite to the first conductivity type, and the first well adjoins the second well to define a p-n junction. The doped region of the second device structure has the first conductivity type or the second conductivity type. The high-resistivity region has a higher electrical resistivity than the semiconductor substrate, and the high-resistivity region is positioned between the first device structure and the second device structure.

公开(公告)号：US20240088157A1

公开(公告)日：2024-03-14

申请号：US17942233

申请日：2022-09-12

Applicant: GlobalFoundries U.S. Inc.

Inventor： Michel Abou-Khalil ,  Steven M. Shank ,  Sarah McTaggart ,  Aaron Vallett ,  Rajendran Krishnasamy ,  Megan Lydon-Nuhfer

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/76286 ,  H01L21/84

Abstract: Semiconductor device structures with device isolation and methods of forming a semiconductor device structure with device isolation. The structure comprises a semiconductor substrate, a first semiconductor layer on the semiconductor substrate, a second semiconductor layer in a cavity in the first semiconductor layer, and a device structure including a doped region in the second semiconductor layer. The first semiconductor layer comprises a porous semiconductor material, and the second semiconductor layer comprises a single-crystal semiconductor material.