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公开(公告)号：WO2017019095A1
公开(公告)日：2017-02-02
申请号：PCT/US2015/042953
申请日：2015-07-30
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： LILLIBRIDGE, Mark David , GOSTIN, Gary , FARABOSCHI, Paolo , SHERLOCK, Derek Alan , RAY, Harvey
CPC classification number: G06F12/0607 , G06F2212/1016
Abstract: In some examples, each processor of a plurality of processors applies an interleave transform to perform interleaved access of a plurality of memory banks, where for any given memory address in use by the plurality of processors, applying any of the interleave transforms results in selection of a same memory bank of the plurality of memory banks and a same address within the same memory bank.
Abstract translation: 在一些示例中，多个处理器的每个处理器应用交织变换来执行多个存储体的交织访问，其中对于多个处理器使用的任何给定存储器地址，应用任何交织变换导致选择 多个存储器组中的相同存储体和相同存储体内相同的地址。
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公开(公告)号：WO2016144362A1
公开(公告)日：2016-09-15
申请号：PCT/US2015/020192
申请日：2015-03-12
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： BALASUBRAMONIAN, Rajeev , LESARTE, Gregg B, , SCHREIBER, Robert , ZAHO, Jishen , MURALIMANOHAR, Naveen , FARABOSCHI, Paolo
CPC classification number: G06F3/064 , G06F3/061 , G06F3/0659 , G06F3/0683 , G06F11/1012 , G06F12/0223 , G06F12/1408 , G06F2212/401 , G11C7/1006 , G11C7/22
Abstract: Techniques for memory device writes based on mapping are provided. In one aspect, a block of data to be written to a line in a rank of memory may be received. The rank of memory may comprise multiple memory devices. The block of data may be written to a number of memory devices determined by the size of the block of data. A memory device mapping for the line may be retrieved. The mapping may determine the order in which the block of data is written to the memory devices within the rank. The block of data may be written to the memory devices based on the mapping.
Abstract translation: 提供了基于映射的存储器件写入技术。 在一个方面，可以接收要写入存储器等级的行的数据块。 存储器的等级可以包括多个存储器设备。 数据块可以写入由数据块的大小确定的多个存储器件。 可以检索用于线路的存储器件映射。 映射可以确定将数据块写入等级内的存储器件的顺序。 可以基于映射将数据块写入存储器件。
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公开(公告)号：WO2016144299A1
公开(公告)日：2016-09-15
申请号：PCT/US2015/019232
申请日：2015-03-06
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： NOVAKOVIC, Stanko , KEETON, Kimberly , FARABOSCHI, Paolo , SCHREIBER, Robert
CPC classification number: G06F17/30368 , G06F17/30578 , G06F17/30958
Abstract: In some examples, a graph processing server is communicatively linked to a shared memory. The shared memory may also be accessible to a different graph processing server. The graph processing server may compute an updated vertex value for a graph portion handled by the graph processing server and flush the updated vertex value to the shared memory, for retrieval by the different graph processing server. The graph processing server may also notify the different graph processing server indicating that the updated vertex value has been flushed to the shared memory.
Abstract translation: 在一些示例中，图形处理服务器通信地链接到共享存储器。 共享存储器也可以被不同的图形处理服务器访问。 图形处理服务器可以计算由图形处理服务器处理的图形部分的更新的顶点值，并将更新的顶点值刷新到共享存储器，以供不同的图形处理服务器检索。 图形处理服务器还可以通知不同的图形处理服务器指示更新的顶点值已被刷新到共享存储器。
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14.发明申请RESPONSIVE SERVER IDENTIFICATION AMONG MULTIPLE DATA SERVERS LINKED TO A SHARED MEMORY 审中-公开连接到共享存储器的多个数据服务器中的响应服务器标识
公开(公告)号：WO2016137496A1
公开(公告)日：2016-09-01
申请号：PCT/US2015/018019
申请日：2015-02-27
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： NOVAKOVIC, Stanko , FARABOSCHI, Paolo , KEETON, Kimberly , ZHAO, Jishen , SCHREIBER, Robert
IPC: G06F15/16 , G06F15/167
CPC classification number: G06F9/505 , H04L67/1008 , H04L69/322
Abstract: In some examples, a method may be performed by server selection circuitry in a device. The method may include sending a first data query to multiple data servers, the multiple data servers linked to a shared memory storing data requested by the first data query. The method may also include tracking response times for the multiple data servers, where the response times include a particular response time for each of the multiple data servers to service the first data query, identifying a responsive server from among the multiple data servers according to the response times, and sending a second data query to the responsive server.
Abstract translation: 在一些示例中，可以由设备中的服务器选择电路执行方法。 该方法可以包括向多个数据服务器发送第一数据查询，链接到共享存储器的多个数据服务器存储由第一数据查询请求的数据。 该方法还可以包括跟踪多个数据服务器的响应时间，其中响应时间包括多个数据服务器中的每一个服务于第一数据查询的特定响应时间，根据该数据服务器从多个数据服务器中识别响应服务器 响应时间，并向响应服务器发送第二个数据查询。
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公开(公告)号：EP2992438B1
公开(公告)日：2019-08-28
申请号：EP13883839.6
申请日：2013-04-30
Applicant: Hewlett Packard Enterprise Development LP
Inventor： LI, Sheng , JOUPPI, Norman Paul , FARABOSCHI, Paolo , KRAUSE, Michael R.
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Patent Agency Ranking
公开(公告)号：EP3271827A1
公开(公告)日：2018-01-24
申请号：EP15899851.8
申请日：2015-07-29
Applicant: Hewlett Packard Enterprise Development LP
Inventor： LILLIBRIDGE, Mark , FARABOSCHI, Paolo , DALTON, Chris I.
IPC: G06F12/14
CPC classification number: G06F21/70 , G06F3/0622 , G06F3/0659 , G06F3/0673 , G06F21/53 , G06F21/74
Abstract: Techniques for a firewall to determine access to a portion of memory are provided. In one aspect, an access request to access a portion of memory within a pool of shared memory may be received at a firewall. The firewall may determine whether the access request to access the portion of memory is allowed. The access request may be allowed to proceed based on the determination. The operation of the firewall may not utilize address translation.
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公开(公告)号：EP3256947A1
公开(公告)日：2017-12-20
申请号：EP15890946.5
申请日：2015-04-30
Applicant: Hewlett Packard Enterprise Development LP
Inventor： LILLIBRIDGE, Mark David , FARABOSCHI, Paolo
CPC classification number: G06F12/1036 , G06F12/023 , G06F12/0292 , G06F12/0804 , G06F2212/1012 , G06F2212/1016 , G06F2212/1041 , G06F2212/302 , G06F2212/455 , G06F2212/657
Abstract: Apertures of a first size in a first physical address space of at least one processor are mapped to respective blocks of the first size in a second address space of a storage medium. Apertures of a second size in the first physical address space are mapped to respective blocks of the second size in the second address space, the second size being different from the first size.
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公开(公告)号：EP2820548B1
公开(公告)日：2016-12-14
申请号：EP12869720.8
申请日：2012-03-02
Applicant: Hewlett Packard Enterprise Development LP
Inventor： YOON, Doe Hyun , CHANG, Jichuan , MURALIMANOHAR, Naveen , SCHREIBER, Robert , FARABOSCHI, Paolo , RANGANATHAN, Parthasarathy
CPC classification number: G06F11/1407 , G06F11/1072 , G06F11/1435 , G06F11/1451 , G06F11/1471 , G06F12/0238 , G06F2212/1016 , G06F2212/1032 , G06F2212/7202 , G06F2212/7209 , G11C11/5621 , G11C2211/5641
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公开(公告)号：EP3063627A1
公开(公告)日：2016-09-07
申请号：EP13896796.3
申请日：2013-10-31
Applicant: Hewlett Packard Enterprise Development LP
Inventor： EDWARDS, Nigel , DALTON, Chris I. , FARABOSCHI, Paolo
IPC: G06F11/00
CPC classification number: G06F21/64 , G06F12/1416 , G06F21/52 , G06F21/566 , G06F21/6218 , G06F21/79 , G06F2212/1052
Abstract: According to an example, memory integrity checking may include receiving computer program code, and using a loader to load the computer program code in memory. Memory integrity checking may further include verifying the integrity of the computer program code by selectively implementing synchronous verification and/or asynchronous verification. The synchronous verification may be based on loader security features associated with the loading of the computer program code. Further, the asynchronous verification may be based on a media controller associated with the memory containing the computer program code.
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公开(公告)号：EP2842036B1
公开(公告)日：2019-07-03
申请号：EP12875252.4
申请日：2012-04-27
Applicant: Hewlett Packard Enterprise Development LP
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