公开(公告)号：GB2430515A

公开(公告)日：2007-03-28

申请号：GB0623489

申请日：2005-06-07

Applicant: HRL LAB LLC

Inventor： SHU DAVID B ,  CHOW LAP-WAI ,  CLARK WILLIAM M JR

IPC: G06F21/02 ,  G06F1/00 ,  G06F9/30 ,  G06F9/38 ,  G06F11/30 ,  G06F21/00 ,  H04L9/00 ,  H04L9/06

Abstract: An apparatus and method for preventing information leakage attacks that utilize timeline alignment. The apparatus and method inserts a random number of instructions into an encryption algorithm such that the leaked information can not be aligned in time to allow an attacker to break the encryption.

公开(公告)号：GB2445652B

公开(公告)日：2009-02-25

申请号：GB0724643

申请日：2005-06-07

Applicant: HRL LAB LLC

Inventor： SHU DAVID B ,  CHOW LAP-WAI ,  CLARK WILLIAM M JR

IPC: G06F21/00 ,  G06F1/00 ,  G06F9/30 ,  G06F9/38 ,  G06F11/30 ,  G06F21/02 ,  H04L9/00 ,  H04L9/06

Abstract: An apparatus and method for preventing information leakage attacks through a polarized cryptographic bus architecture. The polarized cryptographic bus architecture randomly changes the polarity of the target bit such that the leaked information cannot be consistently averaged to yield statistical key material. Further, to increase the prevention of information leakage attacks, a set of dual rails is used to write data to a given register bit.

公开(公告)号：GB2447795A

公开(公告)日：2008-09-24

申请号：GB0807135

申请日：2005-06-07

Applicant: HRL LAB LLC

Inventor： SHU DAVID B ,  CHOW LAP-WAI ,  CLARK WILLIAM M JR

IPC: G06F21/00 ,  G06F1/00 ,  G06F9/30 ,  G06F9/38 ,  G06F11/30 ,  G06F21/02 ,  H04L9/00 ,  H04L9/06

Abstract: The invention prevents information leakage attacks that utilise timeline alignment such as Differential Power Analysis (DPA). A random or predetermined number of pseudo instructions are inserted into an encryption algorithm such that the leaked information cannot be aligned in time to allow an attacker to break the encryption. The pseudo instructions mimic real instructions in terms of energy consumption without affecting the running of the encryption algorithm. The algorithm may be a Data Encryption Standard (DES) algorithm and the pseudo instructions may emulate bit-wise shift instructions. The pseudo instructions may be inserted in substitution/permutation box entry address evaluations. The pseudo instructions may be performed when a control flag is set, the control flag halting a state machine of a processor running the encryption algorithm. The halting of the state machine may comprise disabling a destination register of the state machine. Other embodiments are disclosed, including a cryptographic bus architecture that prevents usage of side channel information by randomly toggling the polarity of a target bit at a data bus driver.