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    CMOS PROCESS
    1.
    发明申请
    CMOS PROCESS 审中-公开
    CMOS工艺

    公开(公告)号：WO02103785A3

    公开(公告)日：2003-08-14

    申请号：PCT/US0219074

    申请日：2002-06-13

    Applicant: HRL LAB LLC ,  BAUKUS JAMES P ,  CHOW LAP-WAI ,  CLARK WILLIAM M JR

    Inventor： BAUKUS JAMES P ,  CHOW LAP-WAI ,  CLARK WILLIAM M JR

    IPC: H01L21/768 ,  H01L27/02 ,  H01L21/8234 ,  H01L23/58 ,  H01L27/088

    CPC classification number: H01L27/02 ,  H01L21/76895 ,  H01L27/0203

    Abstract: An integrated circuit structure for MOS-type devices comprising a silicon substrate of a first conductivity type; a first gate insulating regions selectivelyplaced over the silicon substrate of the first conductivity type; a first polycrystallinesilicon layer selectively placed over the silicon substrate of the first conductivity type;a second gate insulating regions selectively placed over the first gate insulating regionsand the first polycrystalline silicon layer; a second polycrystalline silicon layer selectivelyplaced over the second gate insulating regions; first buried silicon regions of a second conductivity type, buried within the silicon substrate of the first conductivity type, placedunder the first polycrystalline silicon layer and in contact therewith; and second buriedsilicon regions of the second conductivity type, buried within the silicon substrate of the first conductivity type, placed under the second gate insulating regions, under the secondpolycrystalline silicon layer and insulated therefrom.

    Abstract translation: 一种用于MOS器件的集成电路结构，包括第一导电类型的硅衬底; 选择性地放置在第一导电类型的硅衬底上的第一栅绝缘区; 选择性地放置在第一导电类型的硅衬底上的第一多晶硅层;选择性地放置在第一栅极绝缘区域和第一多晶硅层上的第二栅极绝缘区域; 选择性地放置在第二栅绝缘区上的第二多晶硅层; 第一导电类型的第一掩埋硅区域，埋在第一导电类型的硅衬底内，放置在第一多晶硅层之下并与其接触; 以及第二导电类型的第二掩埋硅区域，其被埋置在第二导电类型的硅衬底内，放置在第二栅极绝缘区域下方，在第二多晶硅层下方并与其绝缘。

    Cryptographic bus architecture for preventing Differential Power attacks (DPA)
    5.
    发明专利
    Cryptographic bus architecture for preventing Differential Power attacks (DPA) 未知

    公开(公告)号：GB2449576A

    公开(公告)日：2008-11-26

    申请号：GB0814566

    申请日：2005-06-07

    Applicant: HRL LAB LLC

    Inventor： SHU DAVID B ,  CHOW LAP-WAI ,  CLARK WILLIAM M JR

    IPC: G06F21/00 ,  G06F1/00 ,  G06F9/30 ,  G06F9/38 ,  G06F11/30 ,  G06F21/02 ,  H04L9/00 ,  H04L9/06

    Abstract: A cryptographic bus architecture prevents usage of side channel information by Differential Power Attacks (DPA) by randomly toggling the polarity of an encrypted bit at a data bus driver. The bus architecture comprises bi-directional drivers 315, 317 connected by a bus 316. An N-bit random number generator 313 has N outputs 314, wherein each output comprises one bit. The value of each random bit is used to toggle a driver, i.e. change its polarity, and drive the internal bus so as to defeat correlation. The chance of having a "0" or "1" will be approximately 0.5 due to the randomization of the polarity. Preferably the polarity control line is probe-resistant. The bus may have dual rails for parallel transmission of each bit, with one rail being inverted compared to the other rail to mask power consumption (fig. 14). Other embodiments are disclosed for preventing information leakage attacks that utilise timeline alignment, including inserting a random number of instructions into an encryption algorithm such that the leaked information cannot be aligned in time to allow attacker to break the encryption.

    Multilayered integrated circuit with non functional conductive traces
    9.
    发明专利
    Multilayered integrated circuit with non functional conductive traces 未知

    公开(公告)号：AU2003284270A8

    公开(公告)日：2004-05-13

    申请号：AU2003284270

    申请日：2003-10-16

    Applicant: PROMTEK ,  HRL LAB LLC

    Inventor： BAUKUS JAMES P ,  CHOW LAP-WAI ,  CLARK WILLIAM M JR ,  YANG PAUL OU

    IPC: H01L23/04 ,  H01L23/48 ,  H01L23/52 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58 ,  H01L27/02 ,  H01L29/40

    Abstract: A multilayered integrated circuit and a method of designing a multilayered integrated circuit are provided. The circuit comprises at least two conductive layers and extraneous conductive lines placed in the conductive layers. The extraneous conductive lines are made of a material which is the same as the material in the conductive layers and have dimensions which are the same as the dimension of the material in the conductive layers. The extraneous conductive lines perform functions which are unnecessary to the operation of the integrated circuit and are undistinguishable from the functional conductive lines, thus burdening the work of a reverse engineer. The method of designing the multilayered circuit comprises a step of providing a computer generated representation of the extraneous conductive lines.

    Semiconductor chip with improved resistance to reverse engineering
    10.
    发明专利
    Semiconductor chip with improved resistance to reverse engineering 未知

    公开(公告)号：GB2454418B

    公开(公告)日：2011-06-29

    申请号：GB0903035

    申请日：2007-09-20

    Applicant: HRL LAB LLC ,  RAYTHEON CO ,  PROMTEK

    Inventor： CLARK WILLIAM M JR ,  CHOW LAP WAI ,  HARBISON GAVIN ,  OUYANG PAUL

    IPC: H01L27/02 ,  H01L23/58 ,  H01L29/78

    Abstract: A technique for and structures for camouflaging an integrated circuit structure and strengthen its resistance to reverse engineering. A plurality of transistors are formed in a semiconductor substrate, at least some of the transistors being of the type having sidewall spacers with LDD regions formed under the sidewall spacers. Transistors are programmably interconnected with ambiguous interconnection features, the ambiguous interconnection features each comprising a channel formed in the semiconductor substrate with preferably the same dopant density as the LDD regions, with selected ones of the channels being formed of a conductivity type supporting electrical communication between interconnected active regions and with other selected ones of the channels being formed of a conductivity type inhibiting electrical communication but ambiguously appearing to a reverse engineer as supporting electrical communication.

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