中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

13 records (took 0.022 seconds)

    Cryptographic bus architecture for preventing Differential Power attacks (DPA)
    1.
    发明专利
    Cryptographic bus architecture for preventing Differential Power attacks (DPA) 未知

    公开(公告)号：GB2449576A

    公开(公告)日：2008-11-26

    申请号：GB0814566

    申请日：2005-06-07

    Applicant: HRL LAB LLC

    Inventor： SHU DAVID B ,  CHOW LAP-WAI ,  CLARK WILLIAM M JR

    IPC: G06F21/00 ,  G06F1/00 ,  G06F9/30 ,  G06F9/38 ,  G06F11/30 ,  G06F21/02 ,  H04L9/00 ,  H04L9/06

    Abstract: A cryptographic bus architecture prevents usage of side channel information by Differential Power Attacks (DPA) by randomly toggling the polarity of an encrypted bit at a data bus driver. The bus architecture comprises bi-directional drivers 315, 317 connected by a bus 316. An N-bit random number generator 313 has N outputs 314, wherein each output comprises one bit. The value of each random bit is used to toggle a driver, i.e. change its polarity, and drive the internal bus so as to defeat correlation. The chance of having a "0" or "1" will be approximately 0.5 due to the randomization of the polarity. Preferably the polarity control line is probe-resistant. The bus may have dual rails for parallel transmission of each bit, with one rail being inverted compared to the other rail to mask power consumption (fig. 14). Other embodiments are disclosed for preventing information leakage attacks that utilise timeline alignment, including inserting a random number of instructions into an encryption algorithm such that the leaked information cannot be aligned in time to allow attacker to break the encryption.

    Cryptographic architecture with instruction masking and other techniques for thwarting differential power analysis
    3.
    发明专利
    Cryptographic architecture with instruction masking and other techniques for thwarting differential power analysis 未知

    公开(公告)号：GB2451359A

    公开(公告)日：2009-01-28

    申请号：GB0816396

    申请日：2005-06-07

    Applicant: HRL LAB LLC

    Inventor： SHU DAVID B ,  CHOW LAP-WAI ,  CLARK WILLIAM M JR

    IPC: G06F21/00 ,  G06F1/00 ,  G06F9/30 ,  G06F9/38 ,  G06F11/30 ,  G06F21/02 ,  H04L9/00 ,  H04L9/06

    Abstract: The invention prevents information leakage attacks that utilise timeline alignment such as Differential Power Analysis (DPA). Data processing in a CPU is concealed by inserting a random number of instruction fetch cycles during execution of a program and, while the random number of instruction fetch cycles are occurring, mimicking the power consumption associated with fetching instructions from memory, executing the instructions in program sequence, and writing results to memory registers. The mimicking of power consumption is achieved by the inclusion of an additional dummy register 222, an additional AND gate to emulate AND gates 221 associated with conventional registers 221, and a pseudo program counter 232 to emulate the operation of an actual program counter 230. At the conclusion of the random number of instructions, normal program execution recommences by re-fetching the same instructions which were initially fetched but this time updating memory locations in the normal way. The insertion of the random number of instruction fetch cycles is controlled by a Random Instruction Mask (RIM) control flag 202. Other embodiments are disclosed, including a cryptographic bus architecture that prevents usage of side channel information by randomly toggling the polarity of a target bit at a data bus driver.

    Cryptographic bus architecture for preventing Differential Power Attacks (DPA)
    5.
    发明专利
    Cryptographic bus architecture for preventing Differential Power Attacks (DPA) 未知

    公开(公告)号：GB2445652A

    公开(公告)日：2008-07-16

    申请号：GB0724643

    申请日：2005-06-07

    Applicant: HRL LAB LLC

    Inventor： SHU DAVID B ,  CHOW LAP-WAI ,  CLARK WILLIAM M JR

    IPC: G06F21/00 ,  G06F1/00 ,  G06F9/30 ,  G06F9/38 ,  G06F11/30 ,  G06F21/02 ,  H04L9/00 ,  H04L9/06

    Abstract: The cryptographic bus architecture prevents usage of side channel information by Differential Power Attacks (DPA) by randomly toggling the polarity of a target bit at a data bus driver. The bus architecture comprises bi-directional drivers 315, 317 connected by a bus 316. An N-bit random number generator 313 has N outputs 314, wherein each output comprises one bit. The value of each random bit is used to toggle a driver. i.e. change its polarity, and drive the internal bus so as to defeat correlation. The chance of having a "0" or "1" will be approximately 0.5 due to the randomization of the polarity. Preferably the polarity control line is probe-resistant. Other embodiments are disclosed for preventing information leakage attacks that utilise timeline alignment, including inserting a random number of instructions into an encryption algorithm such that the leaked information cannot be aligned in time to allow attacker to break the encryption.

    Cryptographic architecture with instruction masking for thwarting differential power analysis
    10.
    发明专利
    Cryptographic architecture with instruction masking for thwarting differential power analysis 未知

    公开(公告)号：GB2447804A

    公开(公告)日：2008-09-24

    申请号：GB0810628

    申请日：2005-06-07

    Applicant: HRL LAB LLC

    Inventor： SHU DAVID B ,  CHOW LAP-WAI ,  CLARK WILLIAM M JR

    IPC: G06F21/00 ,  G06F1/00 ,  G06F9/30 ,  G06F9/38 ,  G06F11/30 ,  G06F21/02 ,  H04L9/00 ,  H04L9/06

    Abstract: The invention prevents information leakage attacks that utilise timeline alignment such as Differential Power Analysis (DPA). Data processing in a CPU is concealed by inserting a random number of instruction fetch cycles during execution of a program and, while the random number of instruction fetch cycles is occurring, mimicking the power consumption associated with fetching instructions from memory, executing the instructions in program sequence, and writing results to memory registers. The mimicking of power consumption is achieved by fetching and executing instructions but inhibiting the updating of normal memory locations, for example by updating a dummy memory location instead. At the conclusion of the random number of instructions, normal program execution recommences by re-fetching the same instructions which were initially fetched but this time updating memory locations in the normal way. The insertion of the random number of instruction fetch cycles may be controlled by a Random Instruction Mask (RIM) control flag. Other embodiments are disclosed, including a cryptographic bus architecture that prevents usage of side channel information by randomly toggling the polarity of a target bit at a data bus driver.

Patent Agency Ranking