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    CMOS PROCESS
    6.
    发明申请
    CMOS PROCESS 审中-公开
    CMOS工艺

    公开(公告)号：WO02103785A3

    公开(公告)日：2003-08-14

    申请号：PCT/US0219074

    申请日：2002-06-13

    Applicant: HRL LAB LLC ,  BAUKUS JAMES P ,  CHOW LAP-WAI ,  CLARK WILLIAM M JR

    Inventor： BAUKUS JAMES P ,  CHOW LAP-WAI ,  CLARK WILLIAM M JR

    IPC: H01L21/768 ,  H01L27/02 ,  H01L21/8234 ,  H01L23/58 ,  H01L27/088

    CPC classification number: H01L27/02 ,  H01L21/76895 ,  H01L27/0203

    Abstract: An integrated circuit structure for MOS-type devices comprising a silicon substrate of a first conductivity type; a first gate insulating regions selectivelyplaced over the silicon substrate of the first conductivity type; a first polycrystallinesilicon layer selectively placed over the silicon substrate of the first conductivity type;a second gate insulating regions selectively placed over the first gate insulating regionsand the first polycrystalline silicon layer; a second polycrystalline silicon layer selectivelyplaced over the second gate insulating regions; first buried silicon regions of a second conductivity type, buried within the silicon substrate of the first conductivity type, placedunder the first polycrystalline silicon layer and in contact therewith; and second buriedsilicon regions of the second conductivity type, buried within the silicon substrate of the first conductivity type, placed under the second gate insulating regions, under the secondpolycrystalline silicon layer and insulated therefrom.

    Abstract translation: 一种用于MOS器件的集成电路结构，包括第一导电类型的硅衬底; 选择性地放置在第一导电类型的硅衬底上的第一栅绝缘区; 选择性地放置在第一导电类型的硅衬底上的第一多晶硅层;选择性地放置在第一栅极绝缘区域和第一多晶硅层上的第二栅极绝缘区域; 选择性地放置在第二栅绝缘区上的第二多晶硅层; 第一导电类型的第一掩埋硅区域，埋在第一导电类型的硅衬底内，放置在第一多晶硅层之下并与其接触; 以及第二导电类型的第二掩埋硅区域，其被埋置在第二导电类型的硅衬底内，放置在第二栅极绝缘区域下方，在第二多晶硅层下方并与其绝缘。

    CMOS-COMPATIBLE MEM SWITCHES AND METHOD OF MAKING
    9.
    发明申请
    CMOS-COMPATIBLE MEM SWITCHES AND METHOD OF MAKING 审中-公开
    CMOS兼容元件开关及其制造方法

    公开(公告)号：WO0135433A3

    公开(公告)日：2001-12-27

    申请号：PCT/US0023197

    申请日：2000-08-23

    Applicant: HRL LAB LLC

    Inventor： CHOW LAP-WAI ,  HSU TSUNG-YUAN ,  HYMAN DANIEL J ,  LOO ROBERT Y ,  OUYANG PAUL ,  SCHAFFNER JAMES H ,  SCHMITZ ADELE ,  SCHWARTZ ROBERT N

    IPC: B81B3/00 ,  B81C1/00 ,  H01H1/021 ,  H01H1/58 ,  H01H49/00 ,  H01H59/00 ,  H01H50/00

    CPC classification number: B81C1/00246 ,  B81B2201/014 ,  B81C2201/014 ,  B81C2203/0714 ,  B81C2203/0735 ,  H01H1/58 ,  H01H59/0009 ,  H01H2001/0057

    Abstract: A microelectromechanical (MEM) switch is fabricated inexpensively by using processing steps which are standard for fabricating multiple metal layer integrated circuits, such as CMOS. The exact steps may be adjusted to be compatible with the process of a particular foundry, resulting in a device which is both low cost and readily integrable with other circuits. The processing steps include making contacts for the MEM switch from metal plugs which are ordinarily used as viasto connect metal layers which are separated by a dielectric layer. Such contact vias are formed on either side of a sacrificial metallization area, and then the interconnect metallization is removed from between the contact vias, leaving them separated. Dielectric surrounding the contacts is etched back so that they protrude towards each other. Thus, when the contacts are moved towards each other by actuating the MEM switch, they connect firmly without obstruction. Tungsten is typically used to form vias in CMOS processes, and it makes an excellent contact material, but other via metals may also be employed as contacts. Interconnect metallization may be employed for other structural and interconnect needs of the MEM switch, and is preferably standard for the foundry and process used. Various metals and dielectric materials may be used to create the switches, but in a preferred embodiment the interconnect metal layers are aluminum and the dielectric material is SiO2, materials which are fully compatible with standard four-layer CMOS fabrication processes.

    Abstract translation: 通过使用标准制造多个金属层集成电路（如CMOS）的处理步骤，廉价地制造了微机电（MEM）开关。 可以将精确的步骤调整为与特定代工厂的过程兼容，从而导致低成本且易于与其他电路集成的装置。 处理步骤包括从通常用作通过电介质层分离的永久连接的金属层的金属插头形成用于MEM开关的触点。 这种接触通孔形成在牺牲金属化区域的任一侧，然后从接触通孔之间移除互连金属化，使它们分开。 围绕触点的介质被回蚀，使得它们彼此突出。 因此，当通过致动MEM开关使触点彼此移动时，它们牢固地连接而不阻塞。 钨通常用于在CMOS工艺中形成通孔，并且它制成优良的接触材料，但也可以使用其它通孔金属作为接触。 互连金属化可以用于MEM开关的其他结构和互连需求，并且优选地是用于所使用的铸造和工艺的标准。 可以使用各种金属和介电材料来制造开关，但是在优选实施例中，互连金属层是铝，并且介电材料是SiO 2，与标准四层CMOS制造工艺完全兼容的材料。

    Cryptographic bus architecture for preventing Differential Power attacks (DPA)
    10.
    发明专利
    Cryptographic bus architecture for preventing Differential Power attacks (DPA) 未知

    公开(公告)号：GB2449576A

    公开(公告)日：2008-11-26

    申请号：GB0814566

    申请日：2005-06-07

    Applicant: HRL LAB LLC

    Inventor： SHU DAVID B ,  CHOW LAP-WAI ,  CLARK WILLIAM M JR

    IPC: G06F21/00 ,  G06F1/00 ,  G06F9/30 ,  G06F9/38 ,  G06F11/30 ,  G06F21/02 ,  H04L9/00 ,  H04L9/06

    Abstract: A cryptographic bus architecture prevents usage of side channel information by Differential Power Attacks (DPA) by randomly toggling the polarity of an encrypted bit at a data bus driver. The bus architecture comprises bi-directional drivers 315, 317 connected by a bus 316. An N-bit random number generator 313 has N outputs 314, wherein each output comprises one bit. The value of each random bit is used to toggle a driver, i.e. change its polarity, and drive the internal bus so as to defeat correlation. The chance of having a "0" or "1" will be approximately 0.5 due to the randomization of the polarity. Preferably the polarity control line is probe-resistant. The bus may have dual rails for parallel transmission of each bit, with one rail being inverted compared to the other rail to mask power consumption (fig. 14). Other embodiments are disclosed for preventing information leakage attacks that utilise timeline alignment, including inserting a random number of instructions into an encryption algorithm such that the leaked information cannot be aligned in time to allow attacker to break the encryption.

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