Abstract:
PROBLEM TO BE SOLVED: To provide an integrated circuit protected against reverse engineering, and to provide a method of fabricating the same. SOLUTION: A semiconductor device includes: a field oxide layer 4 disposed on a semiconductor substrate having an opening for limiting a contact region of the semiconductor substrate; a metal plug contact 7 disposed on a portion of the field oxide located within the contact region; and a metal 10 connected to the metal plug contact, wherein the metal plug contact contacts the portion of the field oxide layer, and the portion of the field oxide layer insulates the metal plug contact from the contact region. COPYRIGHT: (C)2010,JPO&INPIT
Abstract:
PROBLEM TO BE SOLVED: To provide a technique for and structures for camouflaging an integrated circuit structure against reverse engineering. SOLUTION: The integrated circuit structure is composed of a plurality of layers of material having a controlled outline. A layer of silicide metal is disposed in active areas of the substrate and has a gap over a channel connecting adjacent active areas. The channel has a channel block structure, which appears identical under reverse engineering whether it is made conductive or insulative. COPYRIGHT: (C)2010,JPO&INPIT
Abstract:
PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit (IC) protection method cheep and easy for mounting helpful to make it impossible to actualize reverse engineering of the IC to prevent the reverse engineering of the IC specifically by making a reverse enginner very difficult to finding out the real contact of each source and drain. SOLUTION: A semiconductor device including the IC having a metal trace connected to a field oxide is provided with a reverse engineering protection. The metallization is usually connected to the gate, source, or drain of a circuit but not to an insulated field oxide, so as to make the reverse enginner make a mistake. The method is for forming the device. COPYRIGHT: (C)2008,JPO&INPIT
Abstract:
A device adapted to protect integrated circuits from reverse engineering comprising a part looking like a via connecting two metal layers, but in fact attached only to one metal layer and spaced from the other. Having such "trick" via would force a reverse engineer to think there is a connection where there is none. A method for fabricating such device.
Abstract:
An apparatus and method for preventing information leakage attacks that utilize timeline alignment. The apparatus and method inserts a random number of instructions into an encryption algorithm such that the leaked information can not be aligned in time to allow an attacker to break the encryption.
Abstract:
An integrated circuit structure for MOS-type devices comprising a silicon substrate of a first conductivity type; a first gate insulating regions selectivelyplaced over the silicon substrate of the first conductivity type; a first polycrystallinesilicon layer selectively placed over the silicon substrate of the first conductivity type;a second gate insulating regions selectively placed over the first gate insulating regionsand the first polycrystalline silicon layer; a second polycrystalline silicon layer selectivelyplaced over the second gate insulating regions; first buried silicon regions of a second conductivity type, buried within the silicon substrate of the first conductivity type, placedunder the first polycrystalline silicon layer and in contact therewith; and second buriedsilicon regions of the second conductivity type, buried within the silicon substrate of the first conductivity type, placed under the second gate insulating regions, under the secondpolycrystalline silicon layer and insulated therefrom.
Abstract:
A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed having a well of a first conductivity type under the gate region being disposed adjacent to active regions of a first conductivity type. The well forming an electrical path between the active regions regardless of any reasonable voltage applied to the integrated circuit structure.
Abstract:
Semiconducting devices, including integrated circuits, are protected from reverse engineering by passivation openings made in a passivation layer. When a reverse engineeretches away the passivation layer and typically the first metal layer, underlying metallayers and/or other elements of the device are destroyed making the reverse engineeringall the more difficult. A method for fabricating such devices is also disclosed.
Abstract:
A microelectromechanical (MEM) switch is fabricated inexpensively by using processing steps which are standard for fabricating multiple metal layer integrated circuits, such as CMOS. The exact steps may be adjusted to be compatible with the process of a particular foundry, resulting in a device which is both low cost and readily integrable with other circuits. The processing steps include making contacts for the MEM switch from metal plugs which are ordinarily used as viasto connect metal layers which are separated by a dielectric layer. Such contact vias are formed on either side of a sacrificial metallization area, and then the interconnect metallization is removed from between the contact vias, leaving them separated. Dielectric surrounding the contacts is etched back so that they protrude towards each other. Thus, when the contacts are moved towards each other by actuating the MEM switch, they connect firmly without obstruction. Tungsten is typically used to form vias in CMOS processes, and it makes an excellent contact material, but other via metals may also be employed as contacts. Interconnect metallization may be employed for other structural and interconnect needs of the MEM switch, and is preferably standard for the foundry and process used. Various metals and dielectric materials may be used to create the switches, but in a preferred embodiment the interconnect metal layers are aluminum and the dielectric material is SiO2, materials which are fully compatible with standard four-layer CMOS fabrication processes.
Abstract:
A cryptographic bus architecture prevents usage of side channel information by Differential Power Attacks (DPA) by randomly toggling the polarity of an encrypted bit at a data bus driver. The bus architecture comprises bi-directional drivers 315, 317 connected by a bus 316. An N-bit random number generator 313 has N outputs 314, wherein each output comprises one bit. The value of each random bit is used to toggle a driver, i.e. change its polarity, and drive the internal bus so as to defeat correlation. The chance of having a "0" or "1" will be approximately 0.5 due to the randomization of the polarity. Preferably the polarity control line is probe-resistant. The bus may have dual rails for parallel transmission of each bit, with one rail being inverted compared to the other rail to mask power consumption (fig. 14). Other embodiments are disclosed for preventing information leakage attacks that utilise timeline alignment, including inserting a random number of instructions into an encryption algorithm such that the leaked information cannot be aligned in time to allow attacker to break the encryption.