公开(公告)号：CA2285847A1

公开(公告)日：2000-05-02

申请号：CA2285847

申请日：1999-10-13

Applicant: IBM

Inventor： GLASCO DAVID BRIAN ,  BAUMGARTNER YOANNA ,  CARPENTER GARY DALE ,  ELMAN ANNA ,  FIELDS JAMES STEPHEN ,  DEAN MARK EDWARD

IPC: G06F12/08 ,  G06F15/167

Abstract: A non-uniform memory access (NUMA) computer system includes a plurality of processing nodes coupled to a node interconnect. The plurality of processing nodes include at least a remote processing node, which contains a processor having an associated cache hierarchy, and a home processing node. The home processing node includes a shared system memory containing a plurality of memory granules and a coherence directory that indicates possible coherence states of copies of memory granules among the plurality of memory granules that are stored within at least one processing node other than the home processing node. If the processor within the remote processing node has a reservation for a memory granule among the plurality of memory granules that is not resident within the associated cache hierarchy, the coherence directory associates the memory granule with a coherence state indicating that the reserved memory granule may possibly be held non-exclusively at the remote processing node. In this manner, the coherence mechanism can be utilized to manage processor reservations even in cases in which a reserving processor's cache hierarchy does not hold a copy of the reserved memory granule.

公开(公告)号：CA2349569C

公开(公告)日：2005-04-05

申请号：CA2349569

申请日：1999-12-10

Applicant: IBM

Inventor： DEAN MARK EDWARD ,  ELMAN ANNA ,  BAUMGARTNER YOANNA

IPC: G06F12/00 ,  G06F12/08 ,  G06F15/16

Abstract: A non-uniform memory access (NUMA) computer system includes at least a local processing node and a remote processing node that are each coupled to a node interconnect. The local processing node includes a local interconnect, a processor and a system memory coupled to the local inteconnect, and a node controller interposed between t he local interconnect and the node interconnect. In responce to receipt of a read request from the local interconnect, the node controller speculatively transmits the read request to the remote processing node via the node interconnect. Thereafter, in response to receipt of a response to the read request from the remote processing node, the node controller handles the response in accordance with a resolution of the read request at the local processing node. For example, in one processing scenario, data contained in the response received from the remote processing node is discarded by the node controller if the read request received a Modified Intervention coherency response at the local processing node.

公开(公告)号：DE69906585D1

公开(公告)日：2003-05-08

申请号：DE69906585

申请日：1999-12-10

Applicant: IBM

Inventor： BAUMGARTNER YOANNA ,  DEAN EDWARD ,  ELMAN ANNA

IPC: G06F12/00 ,  G06F12/08 ,  G06F15/16

Abstract: A non-uniform memory access (NUMA) computer system includes at least a local processing node and a remote processing node that are each coupled to a node interconnect. The local processing node includes a local interconnect, a processor and a system memory coupled to the local interconnect, and a node controller interposed between the local interconnect and the node interconnect. In response to receipt of a read request from the local interconnect, the node controller speculatively transmits the read request to the remote processing node via the node interconnect. Thereafter, in response to receipt of a response to the read request from the remote processing node, the node controller handles the response in accordance with a resolution of the read request at the local processing node. For example, in one processing scenario, data contained in the response received from the remote processing node is discarded by the node controller if the read request received a Modified Intervention coherency response at the local processing node.

公开(公告)号：CA2349569A1

公开(公告)日：2000-06-22

申请号：CA2349569

申请日：1999-12-10

Applicant: IBM

Inventor： BAUMGARTNER YOANNA ,  ELMAN ANNA ,  DEAN MARK EDWARD

IPC: G06F12/00 ,  G06F12/08 ,  G06F15/16

Abstract: A non-uniform memory access (NUMA) computer system includes at least a local processing node and a remote processing node that are each coupled to a node interconnect. The local processing node includes a local interconnect, a processor and a system memory coupled to the local inteconnect, and a node controller interposed between the local interconnect and the node interconnect. In responce to receipt of a read request from the local interconnect, the node controller speculatively transmits the read request t o the remote processing node via the node interconnect. Thereafter, in respons e to receipt of a response to the read request from the remote processing node , the node controller handles the response in accordance with a resolution of the read request at the local processing node. For example, in one processin g scenario, data contained in the response received from the remote processing node is discarded by the node controller if the read request received a Modified Intervention coherency response at the local processing node.

公开(公告)号：CA2291401A1

公开(公告)日：2000-06-17

申请号：CA2291401

申请日：1999-12-02

Applicant: IBM

Inventor： BAUMGARTNER YOANNA ,  ELMAN ANNA

IPC: G06F9/52 ,  G06F12/08 ,  G06F12/12 ,  G06F13/16

Abstract: A non-uniform memory access (NUMA) computer system includes first and second processing nodes that are coupled together. The first processing node includes a system memory and first and second processors that each have a respective associated cache hierarchy. The second processing node includes at least a third processor and a system memory. If the cache hierarchy of the first processor holds an unmodified copy of a cache line and receives a request for the cache line from the third processor, the cache hierarchy of the first processor sources the requested cache line to the third processor and retains a copy of the cache line in a Recent coherency state from which the cache hierarchy of the first processor can source the cache line in response to subsequent requests.