公开(公告)号：WO2009061093A2

公开(公告)日：2009-05-14

申请号：PCT/KR2008006336

申请日：2008-10-28

Applicant: IBM ,  IBM KOREA INC ,  PANG LIANG-TECK ,  KUANG JENTE BENEDICT ,  GEBARA FADI HIKMAT ,  KAO JERRY CHANG-JUI ,  NOWKA KEVIN JOHN ,  CARPENTER GARY DALE

Inventor： PANG LIANG-TECK ,  KUANG JENTE BENEDICT ,  GEBARA FADI HIKMAT ,  KAO JERRY CHANG-JUI ,  NOWKA KEVIN JOHN ,  CARPENTER GARY DALE

IPC: G11C29/00

CPC classification number: G11C7/22 ,  G11C7/12 ,  G11C7/222 ,  G11C29/02 ,  G11C29/023 ,  G11C29/14 ,  G11C29/50 ,  G11C29/50012

Abstract: A storage array including a local clock buffer with programmable timing provides a mechanism for evaluating circuit timing internal to the storage array. The local clock buffer can independently adjust the pulse width of a local clock that controls the wordline and local bitline precharge pulses and the pulse width of a delayed clock that controls the global bitline precharge, evaulate and read data latching. The delay between the local clock and the delayed clock can also be adjusted. By varying the pulse widths of the local and delayed clock signal, along with the inter-clock delay, the timing margins of each cell in the array can be evaluated by reading and writing the cell with varying pulse width and clock delay. The resulting evaluation can be used to evaluate timing margin variation within a die, as well variaton from die-to-die and under varying environments, e.g., voltage and temperature variation.

Abstract translation: 包括具有可编程定时的本地时钟缓冲器的存储阵列提供了用于评估存储阵列内部的电路定时的机制。 本地时钟缓冲器可独立调整控制字线和局部位线预充电脉冲的本地时钟的脉冲宽度，以及控制全局位线预充电，延迟和读取数据锁存的延迟时钟的脉冲宽度。 本地时钟和延迟时钟之间的延迟也可以调整。 通过改变本地和延迟时钟信号的脉冲宽度以及时钟间延迟，阵列中每个单元的时序余量可以通过以不同的脉冲宽度和时钟延迟读取和写入单元来评估。 由此产生的评估可用于评估芯片内的时序裕度变化，以及芯片到芯片和变化环境下的变化，例如电压和温度变化。

公开(公告)号：WO2010037815A3

公开(公告)日：2010-08-05

申请号：PCT/EP2009062758

申请日：2009-10-01

Applicant: IBM ,  IBM UK ,  PANG LIANG-TECK ,  KUANG JENTE BENEDICT ,  CARPENTER GARY DALE ,  NOWKA KEVIN JOHN

Inventor： PANG LIANG-TECK ,  KUANG JENTE BENEDICT ,  CARPENTER GARY DALE ,  NOWKA KEVIN JOHN

IPC: G11C7/22 ,  G11C11/417 ,  G11C11/419

CPC classification number: G11C11/417 ,  G11C7/22 ,  G11C11/419

Abstract: A delay circuit has a fixed delay path at a lower voltage level, a level converter, and an adjustable delay path at a higher voltage level. The fixed delay path includes an inverter chain, and the adjustable delay path includes serially-connected delay elements selectively connected to the circuit output. In an application for a local clock buffer of a static, random- access memory (SRAM), the lower voltage level is that of the local clock buffer, and the higher voltage level is that of the SRAM. These voltages may vary in response to dynamic voltage scaling, requiring re-calibration of the adjustable delay path. The adjustable delay path may be calibrated by progressively increasing the read access time of the SRAM array until a contemporaneous read operation returns the correct output, or by using a replica SRAM path to simulate variations in delay with changes in voltage supply.

Abstract translation: 延迟电路具有在较低电压电平处的固定延迟路径，电平转换器以及在较高电压电平处的可调整延迟路径。 固定延迟路径包括反相器链，并且可调延迟路径包括选择性地连接到电路输出的串联连接的延迟元件。 在用于静态随机存取存储器（SRAM）的本地时钟缓冲器的应用中，较低的电压电平是本地时钟缓冲器的电压电平，并且较高的电压电平是SRAM的电压电平。 这些电压可能随动态电压调整而变化，需要重新校准可调延迟路径。 可以通过逐渐增加SRAM阵列的读取访问时间来校准可调整的延迟路径，直到同时发生的读取操作返回正确的输出为止，或者通过使用复制SRAM路径来模拟随着电压供给的变化而引起的延迟变化。

公开(公告)号：JP2000250884A

公开(公告)日：2000-09-14

申请号：JP2000045976

申请日：2000-02-23

Applicant: IBM

Inventor： CARPENTER GARY DALE ,  MARK EDWARD DEAN ,  DAVID BRIAN GRASCO

IPC: G06F9/52 ,  G06F12/08 ,  G06F15/177

Abstract: PROBLEM TO BE SOLVED: To improve a method for evicting a cache line from a loose directory by writing data from a corrected cache line back to the local system memory of a node and evicting an entry from the loose directory later. SOLUTION: First of all, when corrected data are tried to return to the system memory, a correction intended read (RWITM) transaction can be tried again by any reason except the generation of retry by a processor. In this case, the RWITM transaction is forcedly issued again to a transaction reception unit by an AutoRetry mode. Secondly, it is possible for a corrected cache line to be absent in the remote node 10b and RWITM receives an erasure response. Afterwards, the transaction reception unit of a node controller 20b returns a response to an eviction logic and completes the eviction.

公开(公告)号：JP2000250882A

公开(公告)日：2000-09-14

申请号：JP2000045824

申请日：2000-02-23

Applicant: IBM

Inventor： CARPENTER GARY DALE ,  MARK EDWARD DEAN ,  DAVID BRIAN GRASCO

IPC: G06F12/08 ,  G06F15/177

Abstract: PROBLEM TO BE SOLVED: To avoid a lie block by completing any one of two requests in response to a request from the processor of a first node so as to invalidate the remote copy of a cache line stored in a cache memory. SOLUTION: A first request is selected so as to win (namely, Retry is not received yet). When an invalidation request is transferred to a requested remote node by a node controller 19 on the side of home node, a special bit called AutoRetry bit is set in a transaction. Read (RWITM) intending a correction from the home node 11 is repeated on the side of remote node 12 and Retry is locally performed. When Dclaim request from the remote node 12 is tried again back to a processor 24a, the opportunity to efficiently complete the RWITM request from the home node 11 on a local bus in the remote node 12 is increased.

公开(公告)号：JP2000250881A

公开(公告)日：2000-09-14

申请号：JP2000045748

申请日：2000-02-23

Applicant: IBM

Inventor： CARPENTER GARY DALE ,  DAVID BRIAN GRASCO

IPC: G06F12/08 ,  G06F15/177

Abstract: PROBLEM TO BE SOLVED: To avoid lie block conditions by completing write back on the side of home node without retry only in the case of write back from the owned node of a corrected cache line by a coherence directory in the home node. SOLUTION: The cache coherence directory in a node controller 19 on the side of node 11 can be constructed so as to fetch back a cache line from the owned node for a non-processed request and to simultaneously discriminate time to receive a write back kill (WBC request) from the owned node of the cache line. A READ request is issued again by a processor 14a on the side of home node 11, a system memory 17 supplies effective data and the READ request is efficiently completed by a clean response. The lie block conditions can be avoided. Since the system memory 17 is updated into effective data by the WBC request, data can be supplied.

公开(公告)号：JP2000250883A

公开(公告)日：2000-09-14

申请号：JP2000045925

申请日：2000-02-23

Applicant: IBM

Inventor： JOHN PATON BANNISTER ,  CARPENTER GARY DALE ,  MARK EDWARD DEAN ,  DAVID BRIAN GRASCO ,  RICHARD NICHOLAS IACHETTA JR

IPC: G06F12/08 ,  G06F15/177

Abstract: PROBLEM TO BE SOLVED: To avoid the loss of data and coherence by respectively providing first and second nodes with a local mutual connection, a system memory coupled with the local mutual connection and a node controller located between the local mutual connections. SOLUTION: A READ request in a home node 10a is transferred to a remote node 10b where corrected data are resident. Concerning the READ request, the boat of correction/intervention is received by the remote node 10b. The remote node 10b returns the corrected/intervened boat and the corrected data to the home node 10a. A node controller 20 generates a new tag and issue the write back kill (WBC request) of R bit = 1. A coherence mechanism in the node controller 20 completes the WBC request like ReRum of locally generated WBC requests. In this case, data in a local memory 18 are made effective.

公开(公告)号：JPH1070218A

公开(公告)日：1998-03-10

申请号：JP18543297

申请日：1997-07-10

Applicant: IBM

Inventor： BULLER MARVIN LAWRENCE ,  CARPENTER GARY DALE ,  HOANG BINH THAI

IPC: H05K7/20 ,  H01L23/34 ,  H01L23/467

Abstract: PROBLEM TO BE SOLVED: To reduce thermal stress between a printed circuit board and an integrated circuit package by enabling a convection cooling means in response to an indication of high power state and disabling the convection cooling means in response to an indication of low power state. SOLUTION: A ball grid array packaged integrated circuit 2 is fixed to a printed board 1 and an array of solder balls 3 is connected with an integrated circuit chip 6 through a ceramic package base 4. A heat sink assembly 7 is fixed onto the packaged integrated circuit while being fitted tightly to the integrated circuit 6. The heat sink assembly 7 can be subjected to convection cooling with an air flow 8 upon driving a fan 9. A control switch 11 feeds power to the fan 9 and another fan in the housing of a computer system. The switch 11 enables or disables the fan 9 in response a RUN/SLEEP power management signal being fed on a line 12.

公开(公告)号：GB2464126A

公开(公告)日：2010-04-07

申请号：GB0818192

申请日：2008-10-04

Applicant: IBM

Inventor： CARPENTER GARY DALE ,  GEBARA FADI HIKMAT ,  KAO JERY CHANG-JUI ,  KUANG JENTE BENEDICT ,  NOWKA KEVIN JOHN ,  PANG LIANG-TECK

IPC: G11C7/22 ,  G11C11/413 ,  G11C29/00

Abstract: A storage array is provided with a local clock buffer 18 which produces local clock signal LCLK and delayed local clock signal DELLCLK both with adjustable tunings based upon global clock signal GLK. The adjustment of the local clock signals is provided by control signal(s) ADJUST input into the array. The ADJUST control signal(s) comprise at least one, preferably three, value(s) for setting at least a timing of the local clock signal(s). The local clock buffer can independently adjust the pulse width of a local clock that controls the wordline and local bitline precharge pulses and the pulse width of a delayed clock that controls the global bitline precharge, evaluate and read data latching. The delay between the local clock and the delayed clock can also be adjusted. By varying the pulse widths of the local and delayed clock signal, along with the inter-clock delay, the timing margins of each cell in the array can be evaluated by reading and writing the cell with varying pulse width and clock delay. There is also provided a mechanism and method for evaluating circuit timing internal to the storage array by varying the control value(s) until a point of failure is reached. The resulting evaluation can be used to evaluate timing margin variation within a die, as well variation from die-to-die and under varying environments, e.g., voltage and temperature variation.

公开(公告)号：IE990755A1

公开(公告)日：2000-05-03

申请号：IE990755

申请日：1999-09-07

Applicant: IBM

Inventor： GLASCO DAVID BRIAN ,  JNR RICHARD NICHOLAS IACHETTA ,  CARPENTER GARY DALE ,  DEAN MARK EDWARD

IPC: G06F15/163 ,  G06F12/08

Abstract: A non-uniform memory access (NUMA) data processing system includes a node interconnect to which at least a first processing node and a second processing node are coupled. The first and the second processing nodes each include a local interconnect, a processor coupled to the local interconnect, a system memory coupled to the local interconnect, and a node controller interposed between the local interconnect and the node interconnect. In order to reduce communication latency, the node controller of the first processing node speculatively transmits request transactions received from the local interconnect of the first processing node to the second processing node via the node interconnect. In one embodiment, the node controller of the first processing node subsequently transmits a status signal to the node controller of the second processing node in order to indicate how the request transaction should be processed at the second processing node.

公开(公告)号：DE69119346T2

公开(公告)日：1996-11-07

申请号：DE69119346

申请日：1991-08-29

Applicant: IBM

Inventor： CARPENTER GARY DALE ,  LUNDBERG MARTIN BIRK

IPC: H03F3/30 ,  H03F3/345 ,  H03F3/50 ,  H03K17/16

Abstract: A power amplifier having a power MOS transistor output device. The gate drive for the power device is a bidirectional current source. In one form of the gate driver circuit, the bidirectional current source includes the capability of controlling the limits of the gate current, which in turn controls the slew rate of the power amplifier.