公开(公告)号：IE990755A1

公开(公告)日：2000-05-03

申请号：IE990755

申请日：1999-09-07

Applicant: IBM

Inventor： GLASCO DAVID BRIAN ,  JNR RICHARD NICHOLAS IACHETTA ,  CARPENTER GARY DALE ,  DEAN MARK EDWARD

IPC: G06F15/163 ,  G06F12/08

Abstract: A non-uniform memory access (NUMA) data processing system includes a node interconnect to which at least a first processing node and a second processing node are coupled. The first and the second processing nodes each include a local interconnect, a processor coupled to the local interconnect, a system memory coupled to the local interconnect, and a node controller interposed between the local interconnect and the node interconnect. In order to reduce communication latency, the node controller of the first processing node speculatively transmits request transactions received from the local interconnect of the first processing node to the second processing node via the node interconnect. In one embodiment, the node controller of the first processing node subsequently transmits a status signal to the node controller of the second processing node in order to indicate how the request transaction should be processed at the second processing node.

公开(公告)号：AT232313T

公开(公告)日：2003-02-15

申请号：AT99973434

申请日：1999-11-30

Applicant: IBM

Inventor： CARPENTER GARY DALE ,  DEBACKER PHILIPPE LOUIS ,  DEAN MARK EDWARD ,  GLASCO DAVID BRIAN ,  ROCKHOLD RONALD LYNN

IPC: G06F15/173 ,  G06F9/48 ,  G06F9/46

Abstract: A non-uniform memory access (NUMA) computer system includes at least two nodes coupled by a node interconnect, where at least one of the nodes includes a processor for servicing interrupts. The nodes are partitioned into external interrupt domains so that an external interrupt is always presented to a processor within the external interrupt domain in which the interrupt occurs. Although each external interrupt domain typically includes only a single node, interrupt channeling or interrupt funneling may be implemented to route external interrupts across node boundaries for presentation to a processor. Once presented to a processor, interrupt handling software may then execute on any processor to service the external interrupt. Servicing external interrupts is expedited by reducing the size of the interrupt handler polling chain as compared to prior art methods. In addition to external interrupts, the interrupt architecture of the present invention supports inter-processor interrupts (IPIs) by which any processor may interrupt itself or one or more other processors in the NUMA computer system. IPIs are triggered by writing to memory mapped registers in global system memory, which facilitates the transmission of IPIs across node boundaries and permits multicast IPIs to be triggered simply by transmitting one write transaction to each node containing a processor to be interrupted. The interrupt hardware within each node is also distributed for scalability, with the hardware components communicating via interrupt transactions conveyed across shared communication paths.

公开(公告)号：AU1397600A

公开(公告)日：2000-07-03

申请号：AU1397600

申请日：1999-11-30

Applicant: IBM

Inventor： DEBACKER PHILIPPE LOUIS ,  DEAN MARK EDWARD ,  GLASCO DAVID BRIAN ,  ROCKHOLD RONALD LYNN

IPC: G06F15/173 ,  G06F9/48 ,  G06F9/46

Abstract: A non-uniform memory access (NUMA) computer system includes at least two nodes coupled by a node interconnect, where at least one of the nodes includes a processor for servicing interrupts. The nodes are partitioned into external interrupt domains so that an external interrupt is always presented to a processor within the external interrupt domain in which the interrupt occurs. Although each external interrupt domain typically includes only a single node, interrupt channeling or interrupt funneling may be implemented to route external interrupts across node boundaries for presentation to a processor. Once presented to a processor, interrupt handling software may then execute on any processor to service the external interrupt. Servicing external interrupts is expedited by reducing the size of the interrupt handler polling chain as compared to prior art methods. In addition to external interrupts, the interrupt architecture of the present invention supports inter-processor interrupts (IPIs) by which any processor may interrupt itself or one or more other processors in the NUMA computer system. IPIs are triggered by writing to memory mapped registers in global system memory, which facilitates the transmission of IPIs across node boundaries and permits multicast IPIs to be triggered simply by transmitting one write transaction to each node containing a processor to be interrupted. The interrupt hardware within each node is also distributed for scalability, with the hardware components communicating via interrupt transactions conveyed across shared communication paths.

公开(公告)号：CA2285847A1

公开(公告)日：2000-05-02

申请号：CA2285847

申请日：1999-10-13

Applicant: IBM

Inventor： GLASCO DAVID BRIAN ,  BAUMGARTNER YOANNA ,  CARPENTER GARY DALE ,  ELMAN ANNA ,  FIELDS JAMES STEPHEN ,  DEAN MARK EDWARD

IPC: G06F12/08 ,  G06F15/167

Abstract: A non-uniform memory access (NUMA) computer system includes a plurality of processing nodes coupled to a node interconnect. The plurality of processing nodes include at least a remote processing node, which contains a processor having an associated cache hierarchy, and a home processing node. The home processing node includes a shared system memory containing a plurality of memory granules and a coherence directory that indicates possible coherence states of copies of memory granules among the plurality of memory granules that are stored within at least one processing node other than the home processing node. If the processor within the remote processing node has a reservation for a memory granule among the plurality of memory granules that is not resident within the associated cache hierarchy, the coherence directory associates the memory granule with a coherence state indicating that the reserved memory granule may possibly be held non-exclusively at the remote processing node. In this manner, the coherence mechanism can be utilized to manage processor reservations even in cases in which a reserving processor's cache hierarchy does not hold a copy of the reserved memory granule.

公开(公告)号：CA2280125A1

公开(公告)日：2000-03-29

申请号：CA2280125

申请日：1999-08-12

Applicant: IBM

Inventor： IACHETTA RICHARD NICHOLAS JR ,  CARPENTER GARY DALE ,  DEAN MARK EDWARD ,  GLASCO DAVID BRIAN

IPC: G06F15/163 ,  G06F12/08 ,  G06F15/173

Abstract: A non-uniform memory access (NUMA) data processing system includes a node interconnect to which at least a first processing node and a second processing node are coupled. The first and the second processing nodes each include a local interconnect, a processor coupled to the local interconnect, a system memory coupled to the local interconnect, and a node controller interposed between the local interconnect and the node interconnect. In order to reduce communication latency, the node controller of the first processing node speculatively transmits request transactions received from the local interconnect of the first processing node to the second processing node via the node interconnect. In one embodiment, the node controller of the first processing node subsequently transmits a status signal to the node controller of the second processing node in order to indicate how the request transaction should be processed at the second processing node.

公开(公告)号：GB2349721B

公开(公告)日：2003-07-30

申请号：GB0000996

申请日：2000-01-18

Applicant: IBM

Inventor： CARPENTER GARY DALE ,  DEAN MARK EDWARD ,  GLASCO DAVID BRIAN

IPC: G06F12/08

Abstract: A non-uniform memory access (NUMA) computer system includes first and second processing nodes that are each coupled to a node interconnect. The first processing node includes a system memory and first and second processors that each have a respective one of first and second cache hierarchies, which are coupled for communication by a local interconnect. The second processing node includes at least a system memory and a third processor having a third cache hierarchy. The first cache hierarchy and the third cache hierarchy are permitted to concurrently store an unmodified copy of a particular cache line in a Recent coherency state from which the copy of the particular cache line can be sourced by shared intervention. In response to a request for the particular cache line by the second cache hierarchy, the first cache hierarchy sources a copy of the particular cache line to the second cache hierarchy by shared intervention utilizing communication on only the local interconnect and without communication on the node interconnect.

公开(公告)号：GB2349721A

公开(公告)日：2000-11-08

申请号：GB0000996

申请日：2000-01-18

Applicant: IBM

Inventor： CARPENTER GARY DALE ,  DEAN MARK EDWARD ,  GLASCO DAVID BRIAN

IPC: G06F12/08

Abstract: A non-uniform memory access (NUMA) data processing system includes first and second processing nodes 8a,8n that are each coupled to a node interconnect 22. The first processing node 8a includes a system memory 18 and first and second processors 10a,10m that each have a respective one of first and second cache hierarchies 14, which are coupled for communication by a local interconnect 16. The second processing node 8n includes at least a system memory and a third processor having a third cache hierarchy. The first cache hierarchy and the third cache hierarchy are permitted to concurrently store an unmodified copy of a particular cache line in a Recent coherency state from which the copy of the particular cache line can be sourced by shared intervention. In response to a request for the particular cache line by the second cache hierarchy, the first cache hierarchy sources a copy of the particular cache line to the second cache hierarchy by shared intervention utilizing communication on only the local interconnect 16 and without communication on the node interconnect 22.

公开(公告)号：BR9903228A

公开(公告)日：2000-10-03

申请号：BR9903228

申请日：1999-06-30

Applicant: IBM

Inventor： CARPENTER GARY DALE ,  DEAN MARK EDWARD ,  GLASCO DAVID BRIAN ,  IACHETTA RICHARD NICHOLAS JR

IPC: G06F15/177 ,  G06F12/08 ,  G06F13/38 ,  G06F15/17 ,  G06F15/16

Abstract: A non-uniform memory access (NUMA) computer system includes an interconnect to which multiple processing nodes (including first, second, and third processing nodes) are coupled. Each of the first, second, and third processing nodes includes at least one processor and a local system memory. The NUMA computer system further includes a transaction buffer, coupled to the interconnect, that stores communication transactions transmitted on the interconnect that are both initiated by and targeted at a processing node other than the third processing node. In response to a determination that a particular communication transaction originally targeting another processing node should be processed by the third processing node, buffer control logic coupled to the transaction buffer causes the particular communication transaction to be retrieved from the transaction buffer and processed by the third processing node. In one embodiment, the interconnect includes a broadcast fabric, and the transaction buffer and buffer control logic form a portion of the third processing node.

公开(公告)号：CA2279138A1

公开(公告)日：2000-02-17

申请号：CA2279138

申请日：1999-07-29

Applicant: IBM

Inventor： GLASCO DAVID BRIAN ,  CARPENTER GARY DALE ,  IACHETTA RICHARD NICHOLAS JR

IPC: G06F15/16 ,  G06F12/08 ,  G06F12/02 ,  G06F9/46

Abstract: A non-uniform memory access (NUMA) computer system includes a node interconnect and a plurality of processing nodes that each contain at least one processor, a local interconnect, a local system memory, and a node controller coupled to both a respective local interconnect and the node interconnect. According to the method of the present invention, a communication transaction is transmitted on the node interconnect from a local processing node to a remote processing node. In response to receipt of the communication transaction by the remote processing node, a response including a coherency response field is transmitted on the node interconnect from the remote processing node to the local processing node. In response to receipt of the response at the local processing node, a request is issued on the local interconnect of the local processing node concurrently with a determination of a coherency response indicated by the coherency response field.

公开(公告)号：CA2280125C

公开(公告)日：2003-01-07

申请号：CA2280125

申请日：1999-08-12

Applicant: IBM

Inventor： GLASCO DAVID BRIAN ,  IACHETTA RICHARD NICHOLAS JR ,  CARPENTER GARY DALE ,  DEAN MARK EDWARD

IPC: G06F15/163 ,  G06F12/08 ,  G06F15/173

Abstract: The invention relates to memory access and provided non-uniform memory acces s (NUMA) data processing system includes a node interconnect to which at least a firs t processing node and a second processing node are coupled. The first and the second processing node s each include a local interconnect, a processor coupled to the local interconnect, a system memory coupled to the local interconnect, and a node controller interposed between the local interconnec t and the node interconnect. In order to reduce communication latency, the node controller of the first processing node speculatively transmits request transactions received from the local interconnect of the first processing node to the second processing node via the node interconnect. In one embodiment, the node controller of the first processing node subsequently transmits a status signal to the node controller of the second processing node in order to indicate how the reques t transaction should be processed at the second processing node.