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    11.
    发明专利
    未知

    公开(公告)号：AT179002T

    公开(公告)日：1999-04-15

    申请号：AT92110130

    申请日：1992-06-16

    Applicant: IBM

    Inventor： BROWN PAUL JOSEPH ,  FREDERICKS KENNETH JAMES SR ,  HEFFERON EUGENE PAUL ,  MERITT ALLAN SAMUEL ,  MOFFITT GERALD THOMAS

    IPC: G06F13/14 ,  G06F13/00 ,  H04L29/00 ,  G06F15/16

    Abstract: A method for acquiring the node identifier of a node in a data processing input/output (I/O) system having a plurality of nodes. This procedure is part of the initialization of each node in the I/O system and may be used to establish the configuration of the I/O system such that if a connection breaks or a fault occurs between nodes, the configuration can be confirmed after the break or fault is corrected. This prevents data from being sent to the wrong device if lines were connected in a different configuration during the correction of a fault. The node identifier is a worldwide-unique identifier such that only one node is identified by a node identifier. The node identifier contains a validity code that specifies if the node identifier is valid. Also disclosed is a retry procedure for retrying the acquisition of a node identifier if the acquired node identifier is not valid, and a deferral procedure which defers the retry procedure if a link is not available.

    15.
    发明专利
    未知

    公开(公告)号：DE2430127A1

    公开(公告)日：1975-01-16

    申请号：DE2430127

    申请日：1974-06-22

    Applicant: IBM

    Inventor： BROWN PAUL JOSEPH ,  SMITH RONALD MORTON

    IPC: G06F12/14 ,  G06F9/46 ,  G06F9/52 ,  G06F12/00 ,  G06F15/16 ,  G06F15/177 ,  G06F9/18 ,  G06F13/06

    Abstract: 1432279 Data processing INTERNATIONAL BUSINESS MACHINES CORP 15 May 1974 [29 June 1973] 21509/74 Heading G4A In a multiprogrammed or multiprocessor system in which a plurality of users (programs or processors 12, 13) share storage 10, data which has been accessed by a user from a location 18 in shared storage is held in a register 22 and after processing by a program, the data originally accessed is compared with the data now in the accessed location 18 and, depending on the result of the comparison, the data in the accessed location 18 is replaced by the result 23 of processing the data or the data in the register 22 is replaced by the data from the accessed location 18. In this way, interlocks which are normally provided can be dispensed with as data which has been modified by an interrupting program, or by a processor of higher priority than the processor which initially accessed the data for processing, replaces the unmodified data so that processing may be repeated with the modified data. A comparator 25 detects whether or not the accessed data has been modified, this being in response to a special Compare & Swap instruction embedded in the program at at the end of a processing sequence, and if inequality (data modified) is found a condition code CC1 is set to cause a conditional branch back to the beginning of the processing sequence. In a multiprocessor system an interlock must be provided to prevent a processor 12 from accessing shared storage while another processor 13 is making the decision whether or not to replace the contents of a location 18 by modified data 23 which has just been generated therein.

    17.
    发明专利
    未知

    公开(公告)号：AT185222T

    公开(公告)日：1999-10-15

    申请号：AT93100833

    申请日：1993-01-21

    Applicant: IBM

    Inventor： BARTOW NEIL GEORGE ,  BROWN PAUL JOSEPH ,  CAPOWSKI ROBERT STANLEY ,  FASANO LOUIS THOMAS ,  GREGG THOMAS ANTHONY ,  SALYER GREGORY ,  SUGRUE PATRICK JOHN ,  WESTCOTT DOUGLAS WAYNE ,  ZEYAK VINCENT PAUL JR

    IPC: H04J3/06 ,  H04L25/02 ,  H04L69/40 ,  H04B1/76 ,  H04L1/16

    Abstract: A system and method for asynchronously transmitting data blocks, in parallel, across multiple fibers in a serial manner. Frame groups are provided as a mechanism to transmit associated data serially on each fiber and tie the data being transmitted together. The frame groups do not have sequence numbers, therefore, the receiver determines which frames are part of a frame group by the arrival times of the individual frames. In one embodiment, the transceivers for each member of the parallel bus asynchronously achieve synchronism at each end of the fiber. Thus the need for a common clock is eliminated. The receivers on each side of the bus determine the relative skew for each conductor by performing skew measurements on a calibration message generated by the transmitters on the other side of the bus. When the skew on all conductors, viewed from both sides of the bus, has been determined, the skew values are exchanged across the bus, thus enabling the transmitters to set proper frame spacing.

    18.
    发明专利
    未知

    公开(公告)号：DE69123104D1

    公开(公告)日：1996-12-19

    申请号：DE69123104

    申请日：1991-06-17

    Applicant: IBM

    Inventor： BROWN PAUL JOSEPH ,  ELLIOTT JOSEPH CHARLES ,  HOPPE KARL HELMUTH ,  LYNCH KENNETH ROBERT ,  SACHS MARTIN WILLIAM

    IPC: G06F13/14 ,  G06F13/40

    Abstract: A computer I/O system which includes a dynamic switch (10) having a plurality of ports (P) and a plurality of link-level facilities, with each link-level facility being attached to an individual one of the ports (P). Whenever the state of a port (P) or its attached link-level facility is changed in such a way that the attached link-level facility's ability to communicate with another link-level facility might be affected, this fact is recognized by a dynamic switch control unit (20) which causes a state change notification (SCN) frame to be transmitted to all other link-level facilities which might be affected. The link-level facilities receiving such a state change notification then determine if any of the associations or potential associations with the link-level facility which caused the state change notification are affected.

    HIGH PERFORMANCE CHANNELS FOR DATA PROCESSING SYSTEMS BUS
    20.
    发明专利
    HIGH PERFORMANCE CHANNELS FOR DATA PROCESSING SYSTEMS BUS 未知

    公开(公告)号：CA2089771C

    公开(公告)日：1996-10-01

    申请号：CA2089771

    申请日：1993-02-18

    Applicant: IBM

    Inventor： BARTOW NEIL GEORGE ,  BROWN PAUL JOSEPH ,  CAPOWSKI ROBERT STANLEY ,  FASANO LOUIS THOMAS ,  GREGG THOMAS ANTHONY ,  SALYER GREGORY ,  WESTCOTT DOUGLAS WAYNE

    IPC: G06F13/00 ,  G06F13/12 ,  G06F13/38 ,  H04L69/40 ,  G06F13/14

    Abstract: Buffers are provided in two elements between which data is to be transferred wherein both buffers are managed solely by the originator of the data transfer. Only one transfer is required to transmit a message, and a second transfer acknowledges the completion of the function because message delivery to the receiver is guaranteed under the implemented protocol. When a request is sent, a message timer is started at the sender. When the normal response for the request is received, the timer is reset; however, if the duration of the message operation exceeds the timeout value, a message-timeout procedure is initiated. When the cancel command is issued, a second timer is set. If this timer is exceeded, subsequent cancel commands can be issued. If subsequent cancel commands are issued, a cancel complete command must be sent and responded to. Since the commands must be executed in the sequence in which they are received, a response to the cancel complete command ensures that there are no other cancel operation commands remaining in the receiver, allowing subsequent operations to start without danger of being canceled.

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