公开(公告)号：JP2004220581A

公开(公告)日：2004-08-05

申请号：JP2003421698

申请日：2003-12-18

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ARIMILLI RAVI KUMAR ,  CARGNONI ROBERT ALAN ,  GUY LYNN GUTHRIE ,  STARKE WILLIAM JOHN

IPC: G06F12/08 ,  G06F3/00 ,  G06F12/02 ,  G06F12/10 ,  G06F13/12 ,  G06F13/14

CPC classification number: G06F13/124 ,  G06F12/0835

Abstract: PROBLEM TO BE SOLVED: To provide an improved processor, a data processing system and a data processing method. SOLUTION: An integrated circuit such as the processor includes a substrate and an integrated circuit element formed in the substrate. The integrated circuit element includes a processor core executing an instruction, an interconnect interface coupled to the processor core and supporting a communication between the processor core and a system interconnect external to the integrated circuit and, at least, a part of an external communication adapter coupled to the processor core and supporting input/output communication via an input/output communication link. COPYRIGHT: (C)2004,JPO&NCIPI

Abstract translation: 要解决的问题：提供改进的处理器，数据处理系统和数据处理方法。 解决方案：诸如处理器的集成电路包括衬底和形成在衬底中的集成电路元件。 集成电路元件包括执行指令的处理器核心，耦合到处理器核心的互连接口，并且支持处理器核心与集成电路外部的系统互连之间的通信，并且至少部分外部通信适配器耦合 到处理器核心并通过输入/输出通信链路支持输入/输出通信。 版权所有（C）2004，JPO＆NCIPI

公开(公告)号：JP2004192622A

公开(公告)日：2004-07-08

申请号：JP2003390008

申请日：2003-11-19

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ARIMILLI RAVI KUMAR ,  CARGNONI ROBERT ALAN ,  WILLIAMS DEREK EDWARD ,  KENNETH LEE WRIGHT

IPC: G06F15/17 ,  G06F9/46 ,  G06F12/02 ,  G06F15/167 ,  G06F15/173 ,  G06F15/76 ,  H04L12/28 ,  H04L12/56

CPC classification number: G06F15/173 ,  H04W28/14

Abstract: PROBLEM TO BE SOLVED: To provide an improved data processing system architecture reducing waiting time of communication between physically separating processors, reducing bus bandwidth consumption, and releasing the bus bandwidth for a general data transfer between the processor and a hierarchical memory system. SOLUTION: The identical processing communication information useful in pipelined multiprocessing or parallel multiprocessing is stored in each processor communication register (PCR). Each processor possesses an exclusive right to store to a sector within each PCR within a cluster network and has continuous access to read the PCR contents of itself. Each processor updates its exclusive sector within all of the PCRs via a private protocol or dedicated wireless network, makes all other processors within the cluster network to be able to quickly see the change within the PCR data and bypasses a cache subsystem. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2004192619A

公开(公告)日：2004-07-08

申请号：JP2003389995

申请日：2003-11-19

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ARIMILLI RAVI KUMAR ,  CARGNONI ROBERT ALAN ,  WILLIAMS DEREK EDWARD ,  KENNETH LEE WRIGHT

IPC: G06F15/17 ,  G06F9/00 ,  G06F9/30 ,  G06F9/52 ,  G06F12/02 ,  G06F15/16 ,  G06F15/167 ,  G06F15/173

CPC classification number: G06F9/30101

Abstract: PROBLEM TO BE SOLVED: To provide an improved data processing system architecture reducing waiting time of communication between physically separating processors, reducing bus bandwidth consumption, and releasing the bus bandwidth for a general data transfer between the processor and a hierarchical memory system. SOLUTION: The identical processing communication information useful in pipelined multiprocessing or parallel multiprocessing is stored in each processor communication register (PCR). Each processor updates its exclusive sector within all of the PCRs, makes all other processors to be able to quickly see the change within the PCR data and bypasses a cache subsystem. BY temporarily restricting access to the information or by forcing all the processors to continuously compete and providing processor communication quickly transferred to all the processors, efficiency of the multiprocessor system can be improved. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2004185604A

公开(公告)日：2004-07-02

申请号：JP2003368033

申请日：2003-10-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： RAVI KUMER ARIMIRRI ,  CARGNONI ROBERT ALAN ,  GUY LYNN GUTHRIE ,  STARKE WILLIAM JOHN

IPC: G06F9/46 ,  G06F9/48 ,  G06F12/08

CPC classification number: G06F12/0815 ,  G06F12/0831

Abstract: PROBLEM TO BE SOLVED: To provide a method and system for minimizing a delay when processing an interruption. SOLUTION: This method and system are for managing stored software state information such as cache memory contents and address conversion information which are not important for executing a process inside a processor. The software state of an idle process is stored in a virtual cache inside a system memory. By snooping a kill-type operation for the virtual cache inside the system memory, the cache coherency of the software state in maintained. COPYRIGHT: (C)2004,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种在处理中断时使延迟最小化的方法和系统。 解决方案：该方法和系统用于管理存储的软件状态信息，例如高速缓存存储器内容和地址转换信息，这些信息对于在处理器内执行处理不重要。 空闲进程的软件状态存储在系统内存中的虚拟缓存中。 通过窥探系统内存中的虚拟缓存的kill-type操作，维护软件状态的高速缓存一致性。 版权所有（C）2004，JPO＆NCIPI

公开(公告)号：JP2004185603A

公开(公告)日：2004-07-02

申请号：JP2003368019

申请日：2003-10-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： RAVI KUMER ARIMIRRI ,  CARGNONI ROBERT ALAN ,  GUY LYNN GUTHRIE ,  STARKE WILLIAM JOHN

IPC: G06F9/38 ,  G06F9/00 ,  G06F9/22 ,  G06F9/30 ,  G06F9/32 ,  G06F9/46 ,  G06F9/48

CPC classification number: G06F9/3863 ,  G06F9/30101 ,  G06F9/322 ,  G06F9/3806 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3885 ,  G06F9/4812

Abstract: PROBLEM TO BE SOLVED: To provide a method and system for minimizing a delay when processing an interruption. SOLUTION: This method and system are for predicting a second level interruption handler (SLIH) for processing then interruption on the basis of history information. The predicted SLIH is speculatively executed at the same time as a first level interruption handler (FLIH) for determining a right SLIH for interruption. When the predicted SLIH is rightly predicted, the FLIH suspends execution of the SLIH called by the FLIH, and the predicted SLIH completes the execution. When the predicted SLIH is wrongly predicted, the execution of the predicted SLIH is suspended, and the SLIH called by the FLIH continues till the completion. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：CA2508044C

公开(公告)日：2010-04-13

申请号：CA2508044

申请日：2003-11-14

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  CARGNONI ROBERT ALAN ,  GUTHRIE GUY LYNN ,  STARKE WILLIAM JOHN

IPC: G06F9/22 ,  G06F9/46 ,  G06F9/48 ,  G06F12/00

Abstract: A method and system are disclosed for managing saved process states in a memory of a data processing system that has multiple partitions executing independent operating systems. A hypervisor manager affords access to any processor in the data processing system for the purpose of storing process states for that processor the memory, independent of the operating system running on the processor.

公开(公告)号：AU2003298240A1

公开(公告)日：2004-06-23

申请号：AU2003298240

申请日：2003-11-14

Applicant: IBM

Inventor： CARGNONI ROBERT ALAN ,  GUTHRIE GUY LYNN ,  STARKE WILLIAM JOHN ,  ARIMILLI RAVI KUMAR

IPC: G06F9/22 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F13/24

Abstract: A method and system are disclosed for pre-loading a hard architected state of a next process from a pool of idle processes awaiting execution. When an executing process is interrupted on the processor, a hard architected state, which has been pre-stored in the processor, of a next process is loaded into architected storage locations in the processor. The next process to be executed, and thus its corresponding hard architected state that is pre-stored in the processor, are determined based on priorities assigned to the waiting processes.

公开(公告)号：CA2508044A1

公开(公告)日：2004-06-17

申请号：CA2508044

申请日：2003-11-14

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  CARGNONI ROBERT ALAN ,  STARKE WILLIAM JOHN ,  GUTHRIE GUY LYNN

IPC: G06F9/22 ,  G06F9/46 ,  G06F9/48 ,  G06F12/00

Abstract: A method and system are disclosed for managing saved process states in a memory of a data processing system that has multiple partitions executing independent operating systems. A hypervisor manager affords access to any processor in the data processing system for the purpose of storing process states for that processor the memory, independent of the operating system running on the processor.

公开(公告)号：CA2508041C

公开(公告)日：2011-06-07

申请号：CA2508041

申请日：2003-11-14

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  CARGNONI ROBERT ALAN ,  GUTHRIE GUY LYNN ,  STARKE WILLIAM JOHN

IPC: G06F9/22 ,  G06F9/46 ,  G06F9/30 ,  G06F9/38 ,  G06F13/24

Abstract: A method and system are disclosed for pre-loading a hard architected state of a next process from a pool of idle processes awaiting execution. When an executing process is interrupted on the processor, a hard architected state, which has been pre-stored in the processor, of a next process is loaded into architected storage locations in the processor. The next process to be executed, and thus its corresponding hard architected state that is pre-stored in the processor, are determined based on priorities assigned to the waiting processes.

公开(公告)号：CA2508551C

公开(公告)日：2008-12-16

申请号：CA2508551

申请日：2003-11-14

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  STARKE WILLIAM JOHN ,  GUTHRIE GUY LYNN ,  CARGNONI ROBERT ALAN

IPC: G06F9/06 ,  G06F9/22 ,  G06F9/00 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48 ,  G06F12/02

Abstract: A method and system are disclosed for saving soft state information, which i s non-critical for executing a process in a processor, upon a receipt of a process interrupt by the processor. The soft state is transmitted to a memor y associated with the processor via a memory interface. Preferably, the soft state is transmitted within the processor to the memory interface via a scan - chain pathway within the processor, which allows functional data pathways to remain unobstructed by the storage of the soft state. Thereafter, the stored soft state can be restored from memory when the process is again executed.