公开(公告)号：WO2004051459A3

公开(公告)日：2005-06-30

申请号：PCT/EP0315005

申请日：2003-11-14

Applicant: IBM ,  IBM FRANCE

Inventor： ARIMILLI RAVI KUMAR ,  CARGNONI ROBERT ALAN ,  GUTHRIE GUY LYNN ,  STARKE WILLIAM JOHN

IPC: G06F9/22 ,  G06F9/00 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46

CPC classification number: G06F9/30123 ,  G06F9/30116 ,  G06F9/3013 ,  G06F9/462

Abstract: A method and system are disclosed for saving soft state information, which is non-critical for executing a process in a processor, upon a receipt of a process interrupt by the processor. The soft state is transmitted to a memory associated with the processor via a memory interface. Preferably, the soft state is transmitted within the processor to the memory interface via a scan-chain pathway within the processor, which allows functional data pathways to remain unobstructed by the storage of the soft state. Thereafter, the stored soft state can be restored from memory when the process is again executed.

Abstract translation: 公开了一种方法和系统，用于在接收到处理器的处理中断时，保存对于在处理器中执行处理不重要的软​​状态信息。 软状态经由存储器接口传送到与处理器相关联的存储器。 优选地，软状态在处理器内经由处理器内的扫描链路径在处理器内传送到存储器接口，这允许功能数据路径通过软状态的存储而保持不受阻碍。 此后，当再次执行处理时，可以从存储器恢复存储的软状态。

公开(公告)号：WO2004051471A3

公开(公告)日：2004-07-08

申请号：PCT/EP0315013

申请日：2003-11-14

Applicant: IBM ,  IBM FRANCE

Inventor： ARIMILLI RAVI KUMAR ,  CARGNONI ROBERT ALAN ,  GUTHRIE GUY LYNN ,  STARKE WILLIAM JOHN

IPC: G06F9/22 ,  G06F9/46 ,  G06F9/48 ,  G06F12/00

CPC classification number: G06F9/4812 ,  G06F9/30116 ,  G06F9/3017 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3857

Abstract: A method and system are disclosed for managing saved process states in a memory of a data processing system that has multiple partitions executing independent operating systems. A hypervisor manager affords access to any processor in the data processing system for the purpose of storing process states for that processor the memory, independent of the operating system running on the processor.

Abstract translation: 公开了一种用于管理具有执行独立操作系统的多个分区的数据处理系统的存储器中的保存的处理状态的方法和系统。 虚拟机管理程序管理器可以访问数据处理系统中的任何处理器，以便独立于在处理器上运行的操作系统，为处理器存储该处理器的进程状态。

公开(公告)号：EP0801352A3

公开(公告)日：1998-10-14

申请号：EP97301904

申请日：1997-03-20

Applicant: IBM

Inventor： GUTHRIE GUY LYNN ,  KELLEY RICHARD ALLEN ,  NEAL DANNY MARVIN ,  THURBER STEVE MARK

IPC: G06F13/36 ,  G06F13/40

CPC classification number: G06F13/36 ,  G06F13/4027

Abstract: A data processing system 10 includes a processor 12, system memory 15 and a number of peripheral devices 401, 403, and one or more bridges 400 which may connect between the processor, memory and peripheral devices and other hosts or peripheral devices such as in a network. A bridge, such as a PCI host bridge, connects between a primary bus (e.g system bus) 14 and a secondary bus 16. The host bridge 400 provides a dual host bridge function which creates two secondary bus interfaces. This allows increased loading capability under one dual host bridge compared to a lesser number of slots allowed under one normal host bridge. Also included is additional control logic for providing arbitration control and for steering transactions to the appropriate bus interface. Additionally, peer to peer support across the two secondary bus interfaces is provided.

Abstract translation: 数据处理系统10包括处理器12，系统存储器15和多个外围设备401,403，以及一个或多个桥接器400，其可以连接处理器，存储器和外围设备以及其他主机或外围设备，诸如 网络。 诸如PCI主桥之类的桥连接在主总线（例如系统总线）14和次总线16之间。主桥400提供双主桥功能，其创建两个次级总线接口。 这允许在一个双主桥下增加加载能力，而在一个正常主桥下允许的插槽数量较少。 还包括用于提供仲裁控制和将交易转向相应总线接口的附加控制逻辑。 此外，还提供了跨两个辅助总线接口的对等支持。

公开(公告)号：WO2004051463A3

公开(公告)日：2005-06-02

申请号：PCT/EP0314863

申请日：2003-11-14

Applicant: IBM ,  IBM FRANCE

Inventor： ARIMILLI RAVI KUMAR ,  CARGNONI ROBERT ALAN ,  GUTHRIE GUY LYNN ,  STARKE WILLIAM JOHN

IPC: G06F9/22 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F13/24

CPC classification number: G06F9/30116 ,  G06F9/462

Abstract: A method and system are disclosed for pre-loading a hard architected state of a next process from a pool of idle processes awaiting execution. When an executing process is interrupted on the processor, a hard architected state, which has been pre-stored in the processor, of a next process is loaded into architected storage locations in the processor. The next process to be executed, and thus its corresponding hard architected state that is pre-stored in the processor, are determined based on priorities assigned to the waiting processes.

Abstract translation: 公开了一种用于从等待执行的空闲进程池预加载下一个进程的硬结构状态的方法和系统。 当执行过程在处理器上中断时，下一个进程已被预先存储在处理器中的硬设计状态被加载到处理器中的架构存储位置。 基于分配给等待处理的优先级来确定要执行的下一个进程，并因此其预先存储在处理器中的相应的硬设计状态。

公开(公告)号：JPH1049482A

公开(公告)日：1998-02-20

申请号：JP8420597

申请日：1997-04-02

Applicant: IBM

Inventor： GUTHRIE GUY LYNN ,  KELLEY RICHARD ALLEN ,  NEAL DANNY MARVIN ,  THURBER STEVE MARK

IPC: G06F13/36 ,  G06F13/40

Abstract: PROBLEM TO BE SOLVED: To efficiently process mixed transactions by connecting a 1st secondary bus and a 2nd secondary bus and connecting a bridge to a system bus which generates one logical bus supporting more peripheral devices than a previously set number. SOLUTION: A system 10 connects one host processor 12 to the 1st secondary bus 14 like a system bus that supports many peripheral devices which can be used by a multiprocessor system and also connects the other host processor 12 to the 1st secondary bus 14. Then the host bridge 20A is connected to the 1st secondary bus 14 and the 1st secondary bus 14 and 2nd secondary bus 16 are connected to each other. Further, a system memory 15 is connected to the 1st secondary bus 14 and 30 and 40 as other devices are connected to the 2nd secondary bus 16. Consequently, mixed transactions of the host bridge 20A can efficiently be processed.

公开(公告)号：DE112013000889T5

公开(公告)日：2014-10-16

申请号：DE112013000889

申请日：2013-01-23

Applicant: IBM

Inventor： WILLIAMS DEREK EDWARD ,  GUTHRIE GUY LYNN ,  LE HIEN MINH ,  STUECHELI JEFFREY A

IPC: G06F15/167

Abstract: Ein Mehrfachprozessor-Datenverarbeitungssystem enthält eine Vielzahl von Cachespeichern, die einen Cachespeicher enthalten. Als Reaktion auf ein Erkennen einer speichermodifizierenden Operation durch den Cachespeicher, die eine selbe Zieladresse wie diejenige einer ersten durch den Cachespeicher verarbeiteten Operation des Lesetyps angibt, stellt der Cachespeicher eine Neuversuchsantwort für die speichermodifizierende Operation bereit. Als Reaktion auf den Abschluss der Operation des Lesetyps tritt der Cachespeicher in einen Schiedsrichtermodus ein. Während er sich im Schiedsrichtermodus befindet, erhöht der Cachespeicher vorübergehend dynamisch eine Priorität irgendeiner speichermodifizierenden Operation, die auf die Zieladresse abzielt, im Verhältnis zu irgendeiner zweiten Operation des Lesetyps, die auf die Zieladresse abzielt.

公开(公告)号：DE69736872T2

公开(公告)日：2007-04-26

申请号：DE69736872

申请日：1997-03-20

Applicant: IBM

Inventor： GUTHRIE GUY LYNN ,  KELLEY RICHARD ALLEN ,  NEAL DANNY MARVIN ,  THURBER STEVE MARK

IPC: G06F13/40 ,  G06F13/36

Abstract: A data processing system 10 includes a processor 12, system memory 15 and a number of peripheral devices 401, 403, and one or more bridges 400 which may connect between the processor, memory and peripheral devices and other hosts or peripheral devices such as in a network. A bridge, such as a PCI host bridge, connects between a primary bus (e.g system bus) 14 and a secondary bus 16. The host bridge 400 provides a dual host bridge function which creates two secondary bus interfaces. This allows increased loading capability under one dual host bridge compared to a lesser number of slots allowed under one normal host bridge. Also included is additional control logic for providing arbitration control and for steering transactions to the appropriate bus interface. Additionally, peer to peer support across the two secondary bus interfaces is provided.

公开(公告)号：AU2003298240A8

公开(公告)日：2004-06-23

申请号：AU2003298240

申请日：2003-11-14

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  STARKE WILLIAM JOHN ,  CARGNONI ROBERT ALAN ,  GUTHRIE GUY LYNN

IPC: G06F9/22 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F13/24

Abstract: A method and system are disclosed for pre-loading a hard architected state of a next process from a pool of idle processes awaiting execution. When an executing process is interrupted on the processor, a hard architected state, which has been pre-stored in the processor, of a next process is loaded into architected storage locations in the processor. The next process to be executed, and thus its corresponding hard architected state that is pre-stored in the processor, are determined based on priorities assigned to the waiting processes.

公开(公告)号：SG66462A1

公开(公告)日：1999-07-20

申请号：SG1998000954

申请日：1998-05-06

Applicant: IBM

Inventor： GUTHRIE GUY LYNN ,  RIEK KENNETH ALAN

IPC: G06F13/362 ,  G06F9/46

公开(公告)号：GB2513509B

公开(公告)日：2015-01-14

申请号：GB201414381

申请日：2013-01-22

Applicant: IBM

Inventor： WILLIAMS DEREK EDWARD ,  GUTHRIE GUY LYNN ,  STARKE WILLIAM

IPC: G06F9/30 ,  G06F9/38