公开(公告)号：WO2004051459A3

公开(公告)日：2005-06-30

申请号：PCT/EP0315005

申请日：2003-11-14

Applicant: IBM ,  IBM FRANCE

Inventor： ARIMILLI RAVI KUMAR ,  CARGNONI ROBERT ALAN ,  GUTHRIE GUY LYNN ,  STARKE WILLIAM JOHN

IPC: G06F9/22 ,  G06F9/00 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46

CPC classification number: G06F9/30123 ,  G06F9/30116 ,  G06F9/3013 ,  G06F9/462

Abstract: A method and system are disclosed for saving soft state information, which is non-critical for executing a process in a processor, upon a receipt of a process interrupt by the processor. The soft state is transmitted to a memory associated with the processor via a memory interface. Preferably, the soft state is transmitted within the processor to the memory interface via a scan-chain pathway within the processor, which allows functional data pathways to remain unobstructed by the storage of the soft state. Thereafter, the stored soft state can be restored from memory when the process is again executed.

Abstract translation: 公开了一种方法和系统，用于在接收到处理器的处理中断时，保存对于在处理器中执行处理不重要的软​​状态信息。 软状态经由存储器接口传送到与处理器相关联的存储器。 优选地，软状态在处理器内经由处理器内的扫描链路径在处理器内传送到存储器接口，这允许功能数据路径通过软状态的存储而保持不受阻碍。 此后，当再次执行处理时，可以从存储器恢复存储的软状态。

公开(公告)号：WO2004051471A3

公开(公告)日：2004-07-08

申请号：PCT/EP0315013

申请日：2003-11-14

Applicant: IBM ,  IBM FRANCE

Inventor： ARIMILLI RAVI KUMAR ,  CARGNONI ROBERT ALAN ,  GUTHRIE GUY LYNN ,  STARKE WILLIAM JOHN

IPC: G06F9/22 ,  G06F9/46 ,  G06F9/48 ,  G06F12/00

CPC classification number: G06F9/4812 ,  G06F9/30116 ,  G06F9/3017 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3857

Abstract: A method and system are disclosed for managing saved process states in a memory of a data processing system that has multiple partitions executing independent operating systems. A hypervisor manager affords access to any processor in the data processing system for the purpose of storing process states for that processor the memory, independent of the operating system running on the processor.

Abstract translation: 公开了一种用于管理具有执行独立操作系统的多个分区的数据处理系统的存储器中的保存的处理状态的方法和系统。 虚拟机管理程序管理器可以访问数据处理系统中的任何处理器，以便独立于在处理器上运行的操作系统，为处理器存储该处理器的进程状态。

公开(公告)号：WO2004051463A3

公开(公告)日：2005-06-02

申请号：PCT/EP0314863

申请日：2003-11-14

Applicant: IBM ,  IBM FRANCE

Inventor： ARIMILLI RAVI KUMAR ,  CARGNONI ROBERT ALAN ,  GUTHRIE GUY LYNN ,  STARKE WILLIAM JOHN

IPC: G06F9/22 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F13/24

CPC classification number: G06F9/30116 ,  G06F9/462

Abstract: A method and system are disclosed for pre-loading a hard architected state of a next process from a pool of idle processes awaiting execution. When an executing process is interrupted on the processor, a hard architected state, which has been pre-stored in the processor, of a next process is loaded into architected storage locations in the processor. The next process to be executed, and thus its corresponding hard architected state that is pre-stored in the processor, are determined based on priorities assigned to the waiting processes.

Abstract translation: 公开了一种用于从等待执行的空闲进程池预加载下一个进程的硬结构状态的方法和系统。 当执行过程在处理器上中断时，下一个进程已被预先存储在处理器中的硬设计状态被加载到处理器中的架构存储位置。 基于分配给等待处理的优先级来确定要执行的下一个进程，并因此其预先存储在处理器中的相应的硬设计状态。

公开(公告)号：JP2004318876A

公开(公告)日：2004-11-11

申请号：JP2004112522

申请日：2004-04-06

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BELL JR ROBERT H ,  CARGNONI ROBERT ALAN

IPC: G06F13/372 ,  G06F12/00 ,  G06F12/08 ,  G06F13/14 ,  G06F13/364 ,  G06F13/368

CPC classification number: G06F13/364 ,  G06F12/0846

Abstract: PROBLEM TO BE SOLVED: To manage distributed arbitration for realizing improved performance in a processing system.
SOLUTION: An indicator designating a multi-cycle request is provided to a slice arbiter, and if a multi-cycle request is present, only one slice (first slice) is granted its associated bus. The method further blocks any requests from other requesting slices having a lower latency than the first slice until the latency difference between the other requesting slices and the longest latency slice added to a predetermined cycle counter value has expired. The method also blocks requests from slices having a higher latency than the first slice until the predetermined cycle counter value less the difference in latencies for the first slice and for the higher latency slices has elapsed.
COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JP2004192621A

公开(公告)日：2004-07-08

申请号：JP2003390006

申请日：2003-11-19

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ARIMILLI RAVI KUMAR ,  CARGNONI ROBERT ALAN ,  WILLIAMS DEREK EDWARD ,  KENNETH LEE WRIGHT

IPC: G06F15/17 ,  G06F12/02 ,  G06F15/16 ,  G06F15/167 ,  G06F15/173 ,  H04L12/28 ,  H04L12/42 ,  H04L12/56 ,  H04L29/06 ,  H04L29/08

CPC classification number: H04L69/16 ,  G06F15/17 ,  H04L12/42 ,  H04L67/1002 ,  H04L69/161 ,  H04W28/14

Abstract: PROBLEM TO BE SOLVED: To provide an improved data processing system architecture reducing waiting time of communication between physically separating processors, reducing bus bandwidth consumption, and releasing the bus bandwidth for a general data transfer between the processor and a hierarchical memory system. SOLUTION: Information useful in pipelined multiprocessing or parallel multiprocessing is stored in each processor communication register (PCR). Each processor possesses an exclusive right to store a sector within each PCR and has continuous access to read the contents. Each processor cluster updates its exclusive sector within the PCRs, makes all other processors within the cluster network to be able to quickly see the change within the PCR data and bypasses a cache subsystem. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2004185602A

公开(公告)日：2004-07-02

申请号：JP2003365322

申请日：2003-10-24

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： RAVI KUMER ARIMIRRI ,  CARGNONI ROBERT ALAN ,  GUY LYNN GUTHRIE ,  STARKE WILLIAM JOHN

IPC: G06F9/46 ,  G01R31/3185 ,  G06F9/48 ,  G06F12/00 ,  G06F12/08

CPC classification number: G06F9/462 ,  G01R31/318536 ,  G06F9/30101 ,  G06F9/30116 ,  G06F9/3012 ,  G06F9/3013

Abstract: PROBLEM TO BE SOLVED: To provide a method and system for minimizing a delay when processing an interruption. SOLUTION: This method and system are for managing the hardware architecture state of a processor which is important for executing a process in the processor. When the processor receives the interruption, a shadow copy of the hardware architecture state is stored from the processor into a memory. Since the hardware architecture state can be quickly saved for the interrupted process by the shadow copy of the hardware architecture state, the hardware architecture state of the next process can be soon stored in the processor. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2004318870A

公开(公告)日：2004-11-11

申请号：JP2004103887

申请日：2004-03-31

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CARGNONI ROBERT ALAN ,  GUY LYNN GUTHRIE ,  LIVINGSTON KIRK SAMUEL ,  STARKE WILLIAM JOHN

IPC: G06F12/08 ,  G06F11/08 ,  G06F11/10 ,  G06F12/16 ,  H03M13/29

CPC classification number: G06F11/1064 ,  H03M13/13

Abstract: PROBLEM TO BE SOLVED: To provide a method that corrects an error in an ECC-protected mechanism by applying data with a plurality of bits N to an error correction code (ECC) matrix. SOLUTION: Selected bits are set in an ECC matrix along each row and each column such that encoding for the ECC matrix allows N-bit error correction and (N-1)-bit error detection. The ECC matrix has a set of an odd number of bits in each row. When an error is detected and it is corrected, the data are inverted and then rewritten to a cache array. A corresponding inversion bit for this entry is set to indicate that the data currently stored are inverted. Thereafter, the data are reread from the array, and if the error was due to a hard fault (stuck bit), they will appear correct since the inversion will have changed the value of the defective bit to the stuck value. COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JP2004192620A

公开(公告)日：2004-07-08

申请号：JP2003389998

申请日：2003-11-19

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ARIMILLI RAVI KUMAR ,  CARGNONI ROBERT ALAN ,  WILLIAMS DEREK EDWARD ,  KENNETH LEE WRIGHT

IPC: G06F15/17 ,  G06F9/46 ,  G06F12/02 ,  G06F13/14 ,  G06F15/00 ,  G06F15/16 ,  G06F15/167 ,  G06F15/173 ,  G06F15/76

CPC classification number: G06F15/167

Abstract: PROBLEM TO BE SOLVED: To provide an improved data processing system architecture reducing waiting time of communication between physically separating processors, reducing bus bandwidth consumption, and releasing the bus bandwidth for a general data transfer between the processor and a hierarchical memory system. SOLUTION: The identical processing communication information useful in pipelined multiprocessing or parallel multiprocessing is stored in each processor communication register (PCR). Each processor possesses an exclusive right to store to a sector within each PCR and has continuous access to read PCR contents of itself. Each processor updates its exclusive sector within all of the PCRs using communication over a specialized bus, makes all other processors to be able to quickly see the change within the PCR data and bypasses a cache subsystem. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：AU2003302510A8

公开(公告)日：2004-06-23

申请号：AU2003302510

申请日：2003-11-14

Applicant: IBM

Inventor： CARGNONI ROBERT ALAN ,  ARIMILLI RAVI KUMAR ,  STARKE WILLIAM JOHN ,  GUTHRIE GUY LYNN

IPC: G06F9/22 ,  G06F9/00 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46

Abstract: A method and system are disclosed for saving soft state information, which is non-critical for executing a process in a processor, upon a receipt of a process interrupt by the processor. The soft state is transmitted to a memory associated with the processor via a memory interface. Preferably, the soft state is transmitted within the processor to the memory interface via a scan-chain pathway within the processor, which allows functional data pathways to remain unobstructed by the storage of the soft state. Thereafter, the stored soft state can be restored from memory when the process is again executed.

公开(公告)号：AU2003298240A8

公开(公告)日：2004-06-23

申请号：AU2003298240

申请日：2003-11-14

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  STARKE WILLIAM JOHN ,  CARGNONI ROBERT ALAN ,  GUTHRIE GUY LYNN

IPC: G06F9/22 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F13/24

Abstract: A method and system are disclosed for pre-loading a hard architected state of a next process from a pool of idle processes awaiting execution. When an executing process is interrupted on the processor, a hard architected state, which has been pre-stored in the processor, of a next process is loaded into architected storage locations in the processor. The next process to be executed, and thus its corresponding hard architected state that is pre-stored in the processor, are determined based on priorities assigned to the waiting processes.