公开(公告)号：WO2004051459A3

公开(公告)日：2005-06-30

申请号：PCT/EP0315005

申请日：2003-11-14

Applicant: IBM ,  IBM FRANCE

Inventor： ARIMILLI RAVI KUMAR ,  CARGNONI ROBERT ALAN ,  GUTHRIE GUY LYNN ,  STARKE WILLIAM JOHN

IPC: G06F9/22 ,  G06F9/00 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46

CPC classification number: G06F9/30123 ,  G06F9/30116 ,  G06F9/3013 ,  G06F9/462

Abstract: A method and system are disclosed for saving soft state information, which is non-critical for executing a process in a processor, upon a receipt of a process interrupt by the processor. The soft state is transmitted to a memory associated with the processor via a memory interface. Preferably, the soft state is transmitted within the processor to the memory interface via a scan-chain pathway within the processor, which allows functional data pathways to remain unobstructed by the storage of the soft state. Thereafter, the stored soft state can be restored from memory when the process is again executed.

Abstract translation: 公开了一种方法和系统，用于在接收到处理器的处理中断时，保存对于在处理器中执行处理不重要的软​​状态信息。 软状态经由存储器接口传送到与处理器相关联的存储器。 优选地，软状态在处理器内经由处理器内的扫描链路径在处理器内传送到存储器接口，这允许功能数据路径通过软状态的存储而保持不受阻碍。 此后，当再次执行处理时，可以从存储器恢复存储的软状态。

公开(公告)号：WO2004051471A3

公开(公告)日：2004-07-08

申请号：PCT/EP0315013

申请日：2003-11-14

Applicant: IBM ,  IBM FRANCE

Inventor： ARIMILLI RAVI KUMAR ,  CARGNONI ROBERT ALAN ,  GUTHRIE GUY LYNN ,  STARKE WILLIAM JOHN

IPC: G06F9/22 ,  G06F9/46 ,  G06F9/48 ,  G06F12/00

CPC classification number: G06F9/4812 ,  G06F9/30116 ,  G06F9/3017 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3857

Abstract: A method and system are disclosed for managing saved process states in a memory of a data processing system that has multiple partitions executing independent operating systems. A hypervisor manager affords access to any processor in the data processing system for the purpose of storing process states for that processor the memory, independent of the operating system running on the processor.

Abstract translation: 公开了一种用于管理具有执行独立操作系统的多个分区的数据处理系统的存储器中的保存的处理状态的方法和系统。 虚拟机管理程序管理器可以访问数据处理系统中的任何处理器，以便独立于在处理器上运行的操作系统，为处理器存储该处理器的进程状态。

公开(公告)号：WO2004051463A3

公开(公告)日：2005-06-02

申请号：PCT/EP0314863

申请日：2003-11-14

Applicant: IBM ,  IBM FRANCE

Inventor： ARIMILLI RAVI KUMAR ,  CARGNONI ROBERT ALAN ,  GUTHRIE GUY LYNN ,  STARKE WILLIAM JOHN

IPC: G06F9/22 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F13/24

CPC classification number: G06F9/30116 ,  G06F9/462

Abstract: A method and system are disclosed for pre-loading a hard architected state of a next process from a pool of idle processes awaiting execution. When an executing process is interrupted on the processor, a hard architected state, which has been pre-stored in the processor, of a next process is loaded into architected storage locations in the processor. The next process to be executed, and thus its corresponding hard architected state that is pre-stored in the processor, are determined based on priorities assigned to the waiting processes.

Abstract translation: 公开了一种用于从等待执行的空闲进程池预加载下一个进程的硬结构状态的方法和系统。 当执行过程在处理器上中断时，下一个进程已被预先存储在处理器中的硬设计状态被加载到处理器中的架构存储位置。 基于分配给等待处理的优先级来确定要执行的下一个进程，并因此其预先存储在处理器中的相应的硬设计状态。

公开(公告)号：JP2004318870A

公开(公告)日：2004-11-11

申请号：JP2004103887

申请日：2004-03-31

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CARGNONI ROBERT ALAN ,  GUY LYNN GUTHRIE ,  LIVINGSTON KIRK SAMUEL ,  STARKE WILLIAM JOHN

IPC: G06F12/08 ,  G06F11/08 ,  G06F11/10 ,  G06F12/16 ,  H03M13/29

CPC classification number: G06F11/1064 ,  H03M13/13

Abstract: PROBLEM TO BE SOLVED: To provide a method that corrects an error in an ECC-protected mechanism by applying data with a plurality of bits N to an error correction code (ECC) matrix. SOLUTION: Selected bits are set in an ECC matrix along each row and each column such that encoding for the ECC matrix allows N-bit error correction and (N-1)-bit error detection. The ECC matrix has a set of an odd number of bits in each row. When an error is detected and it is corrected, the data are inverted and then rewritten to a cache array. A corresponding inversion bit for this entry is set to indicate that the data currently stored are inverted. Thereafter, the data are reread from the array, and if the error was due to a hard fault (stuck bit), they will appear correct since the inversion will have changed the value of the defective bit to the stuck value. COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JP2007257631A

公开(公告)日：2007-10-04

申请号：JP2007062831

申请日：2007-03-13

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： GUTHRIE GUY L ,  DEREK E WILLIAMS ,  STARKE WILLIAM JOHN ,  STUECHELI JEFFREY A

IPC: G06F12/08

CPC classification number: G06F12/0831 ,  G06F2212/507

Abstract: PROBLEM TO BE SOLVED: To provide an improved cache coherent data processing system, cache system and method of data processing in a cache coherent data processing system. SOLUTION: A first data-invalid coherency state that indicates that an address tag is valid and that a storage location does not contain valid data is set. In response to snooping an exclusive access request specifying a target address matching the address tag and indicating a relative domain location of the requester that has initiated the exclusive access operation, an update is made to a second data-invalid coherency state that indicates that the address tag is valid, that the storage location does not contain valid data, and whether a target memory block associated with the address tag is cached within a first coherency domain upon successful completion of the exclusive access operation based upon the relative location of the requester. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种改进的高速缓存一致数据处理系统，高速缓存一致数据处理系统中的缓存系统和数据处理方法。

解决方案：设置指示地址标签有效并且存储位置不包含有效数据的第一数据无效一致性状态。 响应于窥探专用访问请求，指定与地址标签匹配的目标地址并指示已经发起独占访问操作的请求者的相对域位置，对第二数据无效一致性状态进行更新，该第二数据无效一致性状态指示地址 标签有效，存储位置不包含有效数据，以及基于请求者的相对位置成功完成独占访问操作后，与地址标签相关联的目标存储器块是否被缓存在第一相干域内。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007193784A

公开(公告)日：2007-08-02

申请号：JP2006341782

申请日：2006-12-19

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： GUY LYNN GUTHRIE ,  STARKE WILLIAM JOHN ,  LEO J CLARK ,  STUECHELI JEFFREY A ,  DEREK EDWARD WILLIAMS

IPC: G06F12/08

CPC classification number: G06F12/0831

Abstract: PROBLEM TO BE SOLVED: To provide an improved cache matching data processing system, a cache system, and a data processing method in the cache matching data processing system. SOLUTION: This cache matching data processing system includes first and second matching domains at least. Inside a first cache memory inside the first matching domain of the data processing system, a memory block is held in a storage position associated with an address tag and a matching state field. It is determined whether a home system memory, to which an address related to a memory block is allocated, is inside the first matching domain or not. If the the home system memory is not inside the first matching domain, the matching state field is set to a matching state showing that the address tag is valid, the storage position includes no valid data, the first matching domain includes no home system memory, and the memory block is cached outside the first matching domain according to formation of the state. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：在缓存匹配数据处理系统中提供改进的高速缓存匹配数据处理系统，缓存系统和数据处理方法。 解决方案：该缓存匹配数据处理系统至少包括第一和第二匹配域。 在数据处理系统的第一匹配域内的第一高速缓冲存储器内部，存储器块被保持在与地址标签和匹配状态字段相关联的存储位置。 确定是否分配了与存储块相关的地址的归属系统存储器在第一匹配域内。 如果家庭系统存储器不在第一匹配域内，则匹配状态字段被设置为表示地址标签有效的匹配状态，存储位置不包括有效数据，第一匹配域不包括家庭系统存储器， 并且根据状态的形成，存储器块被缓存在第一匹配域外。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007287142A

公开(公告)日：2007-11-01

申请号：JP2007099225

申请日：2007-04-05

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： JEFFREY A STUECHELI ,  STARKE WILLIAM JOHN ,  JAMES S FIELDS JR ,  GOODMAN BENJIMAN LEE ,  LEO J CLARK

IPC: G06F15/80 ,  G06F15/173

CPC classification number: G06F12/0831 ,  G06F12/0897 ,  G06F12/1458

Abstract: PROBLEM TO BE SOLVED: To provide an interconnect fabric for a data processing system for saving a bandwidth favorably and improving performance of the whole system. SOLUTION: The data processing system is provided with a plurality of processors coupled by a plurality of communication links for point-to-point communication so that at least a few of communication among a plurality of processing apparatuses out of processors 100 are transmitted via at least one intermediate processor among the plurality of processors. The intermediate processor is provided with: one or more masters for starting a first operation; a snooper for receiving a second operation started by another processor among a plurality of processors; a physical queue for storing the master tag of the first operation started by one or more masters in one of the processors; and a ticket issuing mechanism for assigning to the second operation observed in the intermediate processor a ticket number which indicates the order of observation relative to other second operation. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供用于数据处理系统的互连结构，用于有利地节省带宽并提高整个系统的性能。 解决方案：数据处理系统设置有多个处理器，其通过多个通信链路耦合用于点对点通信，使得在处理器100中的多个处理装置中的至少少数通信被传送 经由多个处理器中的至少一个中间处理器。 中间处理器具有：用于开始第一操作的一个或多个主器件; 用于接收由多个处理器中的另一处理器开始的第二操作的窥探者; 用于存储由一个或多个处理器中的一个处理器中的一个或多个主器件启动的第一操作的主标签的物理队列; 以及票据发行机构，用于将在中间处理器中观察到的第二操作分配给指示相对于其他第二操作的观察次序的票号。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007207223A

公开(公告)日：2007-08-16

申请号：JP2006350414

申请日：2006-12-26

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： GUY LYNN GUTHRIE ,  DEREK EDWARD WILLIAMS ,  STARKE WILLIAM JOHN ,  HOLLAWAY JOHN THOMAS JR

IPC: G06F12/08

CPC classification number: G06F12/0822 ,  G06F12/0804 ,  G06F12/0831

Abstract: PROBLEM TO BE SOLVED: To provide an improved cache-coherent data processing system, and method of data processing. SOLUTION: The data processing system includes at least first and second coherency domains. The first coherency domain receives a broadcast flush operation. The flush operation specifies a target address of a target memory block. The first coherency domain also receives a combined response for the flush operation. In response to receipt in the first coherency domain of the combined response, a determination is made if the combined response indicates that a cached copy of the target memory block may remain within the data processing system. In response to an affirmative determination, a domain indicator is updated to indicate that the target memory block is cached outside of the first coherency domain. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种改进的高速缓存一致性数据处理系统和数据处理方法。 解决方案：数据处理系统至少包括第一和第二相干域。 第一个相干域接收广播冲洗操作。 刷新操作指定目标存储器块的目标地址。 第一个相干域还接收冲洗操作的组合响应。 响应于在组合响应的第一相关域中的接收，确定组合响应是否指示目标存储器块的高速缓存副本可能保留在数据处理系统内。 响应于肯定的确定，域指示符被更新以指示目标存储器块被缓存在第一相干域之外。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2004185602A

公开(公告)日：2004-07-02

申请号：JP2003365322

申请日：2003-10-24

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： RAVI KUMER ARIMIRRI ,  CARGNONI ROBERT ALAN ,  GUY LYNN GUTHRIE ,  STARKE WILLIAM JOHN

IPC: G06F9/46 ,  G01R31/3185 ,  G06F9/48 ,  G06F12/00 ,  G06F12/08

CPC classification number: G06F9/462 ,  G01R31/318536 ,  G06F9/30101 ,  G06F9/30116 ,  G06F9/3012 ,  G06F9/3013

Abstract: PROBLEM TO BE SOLVED: To provide a method and system for minimizing a delay when processing an interruption. SOLUTION: This method and system are for managing the hardware architecture state of a processor which is important for executing a process in the processor. When the processor receives the interruption, a shadow copy of the hardware architecture state is stored from the processor into a memory. Since the hardware architecture state can be quickly saved for the interrupted process by the shadow copy of the hardware architecture state, the hardware architecture state of the next process can be soon stored in the processor. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：AU2003302510A8

公开(公告)日：2004-06-23

申请号：AU2003302510

申请日：2003-11-14

Applicant: IBM

Inventor： CARGNONI ROBERT ALAN ,  ARIMILLI RAVI KUMAR ,  STARKE WILLIAM JOHN ,  GUTHRIE GUY LYNN

IPC: G06F9/22 ,  G06F9/00 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46

Abstract: A method and system are disclosed for saving soft state information, which is non-critical for executing a process in a processor, upon a receipt of a process interrupt by the processor. The soft state is transmitted to a memory associated with the processor via a memory interface. Preferably, the soft state is transmitted within the processor to the memory interface via a scan-chain pathway within the processor, which allows functional data pathways to remain unobstructed by the storage of the soft state. Thereafter, the stored soft state can be restored from memory when the process is again executed.