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    DRIVER CIRCUIT
    12.
    发明专利
    DRIVER CIRCUIT 未知

    公开(公告)号：DE3274696D1

    公开(公告)日：1987-01-22

    申请号：DE3274696

    申请日：1982-02-17

    Applicant: IBM

    Inventor： CHAPPELL BARBARA ALANE ,  SCHUSTER STANLEY EVERETT

    IPC: H03K5/02 ,  G11C8/00 ,  G11C8/08 ,  H03K17/04 ,  H03K17/06 ,  H03K17/687

    Abstract: An FET high performance driver circuit (20) is especially effective in an environment wherein both large input and output capacitive loads are present. The driver includes a push-pull output circuit (30, 40), a clocked load (25), and a switched transfer depletion FET (27) adapted to decouple the large input capacitive load (62) from an internal node (80) of the driver circuit. This switched decoupling allows an isolation of the large input capacitance from the internal node, whereby the internal node potential can be raised rapidly, and the bootstrapping effectiveness at the internal node can be enhanced so as to significantly increase the circuit operating speed in driving large output capacitative load.

    14.
    发明专利
    未知

    公开(公告)号：DE68915608T2

    公开(公告)日：1994-12-01

    申请号：DE68915608

    申请日：1989-03-08

    Applicant: IBM

    Inventor： CHAPPELL BARBARA ALANE ,  LIEN YEONG-CHANG ,  TANG JEFFREY YUH-FONG

    IPC: G11C11/41 ,  G11C8/12 ,  G11C8/00

    Abstract: A transposable memory architecture for providing equally fast access to stored data in two or more dimensions. This architecture is provided by orthogonal wiring of access devices, word lines and bit lines with independent random accessing capability for data in each direction. The transposable memory architecture (TMA) cell directly implements the TMA architecture using only one access device per dimension of access. This invention also describes multiple transposable memory architecture (MTMA) device for additional data path flexibility. The read and write operations described provide access and cycle times approximately equivalent to those for a convention one-dimension RAM.

    15.
    发明专利
    未知

    公开(公告)号：DE68917953D1

    公开(公告)日：1994-10-13

    申请号：DE68917953

    申请日：1989-02-02

    Applicant: IBM

    Inventor： CHAPPELL BARBARA ALANE ,  CHAPPELL TERRY IVAN ,  SCHUSTER STANLEY EVERETT

    IPC: G11C11/413 ,  G11C8/10 ,  G11C11/408 ,  G11C8/00

    Abstract: A high performance decoder/driver circuit for a semiconductor memory having A1 to AN (true) and A1 to AN (complement) address lines for receiving A1 to AN address bit signals thereon from internal address buffers. A phi PC line is included for receiving a phi PC precharge clock signal thereon and a phi R line is provided for receiving a phi R reset clock signal thereon. The decoder/driver circuit includes an OR decoder means having a plurality of transistor switching devices (1-7) connected to A1 to AN-1 or A1 to AN-1 of the true and complement address lines for the AN to AN-1 address bits for producing a high or low level signal on an OR decoder output node (16) depending on the address bits state. The decoder/driver circuit further includes a selection means (8-11) having a plurality of transistor devices including p-channel devices, having diffusion contacts connected to the output node (17, 18) of the decoder and to AN and AN lines to produce a first selection signal when the OR decoder output node is low and the AN line is high and a second selection signal when the OR decoder output node is low and the AN line is high. A driver circuit is connected to the selection means and is responsive to the first selection signal to provide an output signal on a first memory word line (WLi) and is further responsive to the second selection signal to provide an output signal on a second memory word line (WLi+1).

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