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    MANUFACTURE OF DUAL-GATE OXIDE DUAL WORK FUNCTION CMOS
    1.
    发明专利
    MANUFACTURE OF DUAL-GATE OXIDE DUAL WORK FUNCTION CMOS 失效

    公开(公告)号：JPH11317459A

    公开(公告)日：1999-11-16

    申请号：JP2115999

    申请日：1999-01-29

    Applicant: IBM

    Inventor： BRONNER GARY BELA ,  EL-KAREH BADIH ,  SCHUSTER STANLEY EVERETT

    IPC: H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/10 ,  H01L27/108

    Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method for a dual-gate oxide which is capable of manufacturing a single integrated circuit chip, wherein a logic circuit and a DRAM are combined and manufacturing a field effect transistor(FET) having a dual work function. SOLUTION: First, a thick gate oxide layer 104 is formed on a wafer, than a doped polysilicon layer 106, a silicide tungsten layer 108 and a nitride layer 110 are successively laminated on the oxide layer in order to form a gate stack. A part of the stack is selectively removed, and the wafer on which the logic circuits are formed in re-exposed. A thin gate oxide layer 116 is formed on the re-exposed region of the wafer, a polysilicon gate 120 is formed thereon, and a thick oxide NFET and PFET are formed on the gate. A thick oxide device region is selectively changed into a silicide 146, then the gate is etched from the stack in the thick oxide device region. Finally, dopant ions are implanted into source/drain regions 140 and 142 of the thick gate oxide device and are made to diffuse, and a deep junction and a dual work function gate are formed.

    Method for dual gate oxide dual workfunction cmos
    3.
    发明专利
    Method for dual gate oxide dual workfunction cmos 未知

    公开(公告)号：SG70150A1

    公开(公告)日：2000-01-25

    申请号：SG1999000336

    申请日：1999-02-03

    Applicant: IBM

    Inventor： BRONNER GARY BELA ,  EL-KAREH BADIH ,  SCHUSTER STANLEY EVERETT

    IPC: H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/10 ,  H01L27/108

    Abstract: A method of forming integrated circuit chips including two dissimilar type NFETs and/or two dissimilar type PFETs on the same chip, such as both thick and thin gate oxide FETs. A DRAM array may be constructed of the thick oxide FETs and logic circuits may be constructed of the thin oxide FETs on the same chip. First, a gate stack including a first, thick gate SiO2 layer is formed on a wafer. The stack includes a doped polysilicon layer on the gate oxide layer, a silicide layer on the polysilicon layer and a nitride layer on the silicide layer. Part of the stack is selectively removed to re-expose the wafer where logic circuits are to be formed. A thinner gate oxide layer is formed on the re-exposed wafer. Next, gates are formed on the thinner gate oxide layer and thin oxide NFETs and PFETs are formed at the gates. After selectively siliciding thin oxide device regions, gates are etched from the stack in the thick oxide device regions. Finally, source and drain regions are implanted and diffused for the thick gate oxide devices.

    4.
    发明专利
    未知

    公开(公告)号：DE3867964D1

    公开(公告)日：1992-03-05

    申请号：DE3867964

    申请日：1988-07-05

    Applicant: IBM

    Inventor： CHAPPELL BARBARA ALANE ,  CHAPPELL TERRY IVAN ,  SCHUSTER STANLEY EVERETT

    IPC: G11C11/41 ,  G11C7/10 ,  G11C7/12 ,  G11C8/12 ,  G11C11/401 ,  G11C11/413 ,  G11C8/00 ,  G11C7/00

    Abstract: A semiconductor random access memory chip wherein the cycle time is less than the access time for any combination of read or write sequence. The semiconductor random access memory chip is partitioned into relatively small sub-arrays with local decoding (RS, WS) and precharging (BLPC). The memory chip operates in a pipelined manner with more than one access propagating through the chip at any given time and wherein the cycle time is limited by sub-array cycles wherein the cycle time is less than the access time for a memory chip having cycle times greater than access times for accesses through the same sub-array. The memory chip also incorporates dynamic storage techniques for achieving very fast access and precharge times.

    Cache performance improvement through the use of early select techniques and pipelining
    5.
    发明专利
    Cache performance improvement through the use of early select techniques and pipelining 未知

    公开(公告)号：GB2328298B

    公开(公告)日：2002-02-20

    申请号：GB9814444

    申请日：1998-07-06

    Applicant: IBM

    Inventor： MATICK RICHARD EDWARD ,  SCHUSTER STANLEY EVERETT

    IPC: G06F12/08

    Abstract: A DRAM for L2 cache is used in a computer memory hierarchy without compromising overall system performance. By proper organization and design, the DRAM L2 cache is many times larger than a SRAM implementation in the same technology, but without compromising overall system performance. The larger DRAM capacity compared to a SRAM gives a substantially better HIT ratio which compensates for any small degradation due to access time. To achieve this, it is essential to minimize the total DRAM access time as much as possible by the use of early select techniques and pipelining.

    9.
    发明专利
    未知

    公开(公告)号：DE68917953D1

    公开(公告)日：1994-10-13

    申请号：DE68917953

    申请日：1989-02-02

    Applicant: IBM

    Inventor： CHAPPELL BARBARA ALANE ,  CHAPPELL TERRY IVAN ,  SCHUSTER STANLEY EVERETT

    IPC: G11C11/413 ,  G11C8/10 ,  G11C11/408 ,  G11C8/00

    Abstract: A high performance decoder/driver circuit for a semiconductor memory having A1 to AN (true) and A1 to AN (complement) address lines for receiving A1 to AN address bit signals thereon from internal address buffers. A phi PC line is included for receiving a phi PC precharge clock signal thereon and a phi R line is provided for receiving a phi R reset clock signal thereon. The decoder/driver circuit includes an OR decoder means having a plurality of transistor switching devices (1-7) connected to A1 to AN-1 or A1 to AN-1 of the true and complement address lines for the AN to AN-1 address bits for producing a high or low level signal on an OR decoder output node (16) depending on the address bits state. The decoder/driver circuit further includes a selection means (8-11) having a plurality of transistor devices including p-channel devices, having diffusion contacts connected to the output node (17, 18) of the decoder and to AN and AN lines to produce a first selection signal when the OR decoder output node is low and the AN line is high and a second selection signal when the OR decoder output node is low and the AN line is high. A driver circuit is connected to the selection means and is responsive to the first selection signal to provide an output signal on a first memory word line (WLi) and is further responsive to the second selection signal to provide an output signal on a second memory word line (WLi+1).

    10.
    发明专利
    未知

    公开(公告)号：DE3785317T2

    公开(公告)日：1993-10-28

    申请号：DE3785317

    申请日：1987-11-24

    Applicant: IBM

    Inventor： HWANG WEI ,  SCHUSTER STANLEY EVERETT ,  TERMAN LEWIS MADISON

    IPC: G11C11/401 ,  H01L21/74 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H01L21/82

    Abstract: A vertical DRAM structure comprising a VMOS transistor and trench capacitor in combination wherein the access transistors are in a V-groove and the capacitors are in two vertical layers. The structure has only a single level of polysilicon and has no contacts. The memory cell circuit is a one-device memory cell, having a single access transistor with its gate (40) connected to a word line (WL), its drain (30) connected to a bit line (BL), and its source (22) connected to a storage capacitor. More particularly, the storage capacitance node (16) is connected to the source (22) of the V-groove access device through a conducting bridge (e.g. 18). An epitaxial layer (26) is grown over a combination of single crystalline material and oxide. Polycrystalline regions in the silicon substrate have an oxide covering. In an alternate version, a single crystal epitaxial layer is disposed over regions consisting of both single crystal and poly crystal Si or polycrystalline material on top of single crystalline material is converted into single crystalline material.

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