公开(公告)号：DE3784120T2

公开(公告)日：1993-08-12

申请号：DE3784120

申请日：1987-06-30

Applicant: IBM

Inventor： CROUSE WILLIAM GEORGE ,  WARE MALCOLM SCOTT

IPC: G10L19/02 ,  H04B1/66

Abstract: Sub-band speech coders that depend on allocation of available bit capacity of a transmission medium to provide high quality speech coding for digital transmission are well known. The present invention utilizes one or more bit allocation tables to dynamically distribute the channel bit capacity bandwidth among the frequency bands according to the desired output quality of speech rather than by means of complex algorithms or simulation techniques. Multiple bit assignment tables are provided to allow various quality levels to be traded off as increasing bit rate demands are placed upon the transmission system. The technique is used for a single coder to achieve a minimum bit rate for a desired given level of subjective quality in speech output or may be used in a shared bit resource to maintain equal and minimum quality degradation for all users. The quality tables determine the number of bits to be dropped from the encoded representation of each signal sample to minimize the transmission load for a given coder without sacrificing speech quality to an unacceptable degree. Table entries are arranged based on the overall band peak energy level and on the sub-band peak energy distribution or spectrum as it is known in the field.

公开(公告)号：AU4218572A

公开(公告)日：1973-11-15

申请号：AU4218572

申请日：1972-05-11

Applicant: IBM

Inventor： CROUSE WILLIAM GEORGE ,  JONES JOHN EARLE

IPC: G06K7/016 ,  G06K19/06 ,  H04L25/49 ,  G06K9/06 ,  G06K9/13

公开(公告)号：CH643973A5

公开(公告)日：1984-06-29

申请号：CH958778

申请日：1978-09-13

Applicant: IBM

Inventor： CROUSE WILLIAM GEORGE

IPC: H04J3/18 ,  H03M3/02 ,  H04B14/06 ,  H03K13/22

公开(公告)号：DE2836049A1

公开(公告)日：1979-04-26

申请号：DE2836049

申请日：1978-08-17

Applicant: IBM

Inventor： CROUSE WILLIAM GEORGE

IPC: H04J3/18 ,  H03M3/02 ,  H04B14/06 ,  H03K13/22

公开(公告)号：DE2228526A1

公开(公告)日：1973-01-11

申请号：DE2228526

申请日：1972-06-12

Applicant: IBM

Inventor： CROUSE WILLIAM GEORGE ,  JONES JOHN EARLE

IPC: G06K7/016 ,  G06K19/06 ,  H04L25/49 ,  G06K7/14

公开(公告)号：HU219533B

公开(公告)日：2001-05-28

申请号：HU9400792

申请日：1992-08-26

Applicant: IBM

Inventor： CARMON DONALD EDWARD ,  CROUSE WILLIAM GEORGE ,  WARE MALCOLM SCOTT

IPC: G06F9/50 ,  G06F13/28 ,  G06F17/10

Abstract: A multi-media user task (host) computer is interfaced to a high speed DSP which provides support functions to the host computer via an interprocessor DMA bus master and controller. Support of multiple dynamic hard real-time signal processing task requirements are met by posting signal processor support task requests from the host processor through the interprocessor DMA controller to the signal processor and its operating system. The signal processor builds data transfer packet request execution lists in a partitioned queue in its own memory and executes internal signal processor tasks invoked by users at the host system by extracting signal sample data from incoming data packets presented by the interprocessor DMA controller in response to its execution of the DMA packet transfer request queues built by the signal processor in the partitioned queue. Processed signal values etc. are extracted from signal processor memory by the DMA interprocessor controller executing the partitioned packet request lists and delivered to the host processor. A very large number of packet transfers in support of numerous user tasks and implementing a very large number of DMA channels is thus made possible while avoiding the need for arbitration between the channels on the part of the signal processor or the host processor.

公开(公告)号：AT149259T

公开(公告)日：1997-03-15

申请号：AT92918307

申请日：1992-08-26

Applicant: IBM

Inventor： CARMON DONALD EDWARD ,  CROUSE WILLIAM GEORGE ,  WARE MALCOLM SCOTT

IPC: G06F9/50 ,  G06F13/28 ,  G06F17/10 ,  G06F9/46

Abstract: A multi-media user task (host) computer is interfaced to a high speed DSP which provides support functions to the host computer via an interprocessor DMA bus master and controller. Support of multiple dynamic hard real-time signal processing task requirements are met by posting signal processor support task requests from the host processor through the interprocessor DMA controller to the signal processor and its operating system. The signal processor builds data transfer packet request execution lists in a partitioned queue in its own memory and executes internal signal processor tasks invoked by users at the host system by extracting signal sample data from incoming data packets presented by the interprocessor DMA controller in response to its execution of the DMA packet transfer request queues built by the signal processor in the partitioned queue. Processed signal values etc. are extracted from signal processor memory by the DMA interprocessor controller executing the partitioned packet request lists and delivered to the host processor. A very large number of packet transfers in support of numerous user tasks and implementing a very large number of DMA channels is thus made possible while avoiding the need for arbitration between the channels on the part of the signal processor or the host processor.

公开(公告)号：HUT68084A

公开(公告)日：1995-05-29

申请号：HU9400792

申请日：1992-08-26

Applicant: IBM

Inventor： CROUSE WILLIAM GEORGE ,  CARMON DONALD EDWARD ,  WARE MALCOLM SCOTT

IPC: G06F9/50 ,  G06F13/28 ,  G06F17/10

Abstract: A multi-media user task (host) computer is interfaced to a high speed DSP which provides support functions to the host computer via an interprocessor DMA bus master and controller. Support of multiple dynamic hard real-time signal processing task requirements are met by posting signal processor support task requests from the host processor through the interprocessor DMA controller to the signal processor and its operating system. The signal processor builds data transfer packet request execution lists in a partitioned queue in its own memory and executes internal signal processor tasks invoked by users at the host system by extracting signal sample data from incoming data packets presented by the interprocessor DMA controller in response to its execution of the DMA packet transfer request queues built by the signal processor in the partitioned queue. Processed signal values etc. are extracted from signal processor memory by the DMA interprocessor controller executing the partitioned packet request lists and delivered to the host processor. A very large number of packet transfers in support of numerous user tasks and implementing a very large number of DMA channels is thus made possible while avoiding the need for arbitration between the channels on the part of the signal processor or the host processor.

公开(公告)号：DE3680463D1

公开(公告)日：1991-08-29

申请号：DE3680463

申请日：1986-08-05

Applicant: IBM

Inventor： CROUSE WILLIAM GEORGE ,  CUNNINGHAM EARL ALBERT ,  VINAL ALBERT WATSON

IPC: G11B5/58 ,  G11B5/596 ,  G11B21/10

公开(公告)号：DE3066870D1

公开(公告)日：1984-04-12

申请号：DE3066870

申请日：1980-11-20

Applicant: IBM

Inventor： CROUSE WILLIAM GEORGE

IPC: H03M3/02 ,  H03M7/34 ,  H04B14/06 ,  H04B12/04

Abstract: Delay circuits (21) and (22) and logic gates (23, 24, 25) provide an output which is representative of three successive like bits appearing on the compander input line. Multiplier (26) multiplies the current delta step value DELTA by /16 and multiplier (27) multiplies the same by - /64. When the output of logic gate (25) is a 1, (three like bits), AND gate (28) let the output of multiplier (26) apply to three input adder (31). The output of this adder then delivers a delta step signal When the output of logic gate (25) is a zero, the new delta step is since AND gate (28) does not deliver any output. Multipliers (26) and (27) are shift registers, and the division by 16 or 64 is performed by achieving a four (or six) bit right shift and dropping the right most four (or six) bits.