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公开(公告)号：WO2008107344A2
公开(公告)日：2008-09-12
申请号：PCT/EP2008052319
申请日：2008-02-26
Applicant: IBM , IBM UK , BOLAN JOSEPH EDWARD , CAMPBELL KEITH MANDERS , KUMAR VIJAY , WARE MALCOLM SCOTT
Inventor： BOLAN JOSEPH EDWARD , CAMPBELL KEITH MANDERS , KUMAR VIJAY , WARE MALCOLM SCOTT
CPC classification number: G06F1/3203
Abstract: Systems and methods are provided for managing power in a processing system. In one embodiment, a target system having a plurality of electronic devices is operated within a net power limit. A local controller detects power consumption for each device, and communicates the power consumption to a power management module. The power management module dynamically apportions the net power limit among the devices, and communicates the apportioned power limit for each device back to the associated local controller. Each local controller enforces the apportioned power limit to an associated device on behalf of the power management module.
Abstract translation: 提供了用于管理处理系统中的电力的系统和方法。 在一个实施例中，具有多个电子设备的目标系统在净功率极限内运行。 本地控制器检测每个设备的功耗，并将功耗传达给电源管理模块。 电源管理模块动态地分配设备之间的净功率限制，并将每个设备的分摊功率限制传回给相关的本地控制器。 每个本地控制器代表电源管理模块对相关联的设备实施分配的功率限制。
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2.发明专利
公开(公告)号：JP2002344658A
公开(公告)日：2002-11-29
申请号：JP2002078556
申请日：2002-03-20
Applicant: IBM
Inventor： DAVIS GORDON TAYLOR , DERBY JEFFREY HASKELL , ELEFTHERIOU EVANGELOS STAVROS , OELCER SEDAT , WARE MALCOLM SCOTT
Abstract: PROBLEM TO BE SOLVED: To substantially reduce the overall power requirement of a line driver connected to a digital subscriber line DSL by limiting a bandwidth of a signal transmitted to all subscriber lines other than those connected to an intended recipient of a physical data frame. SOLUTION: A shared digital subscriber line modem achieves reduced total power consumption and aquires data security by generating and transmitting a physical data frame which includes a control channel and a data field to only the connected client modem associated with the intended recipient. A second physical frame which does not include the data field is generated and transmitted to all of the other connected client modems.
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3.发明专利Method for managing operation related to voltage and frequency change in microprocessor, data processing system and computer program 有权用于管理与微处理器的电压和频率变化相关的操作的方法，数据处理系统和计算机程序
公开(公告)号：JP2011081800A
公开(公告)日：2011-04-21
申请号：JP2010225316
申请日：2010-10-05
Applicant: Internatl Business Mach Corp
, インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation Inventor： RUBIO JUAN CARLOS , RAJAMANI KARTHICK , WARE MALCOLM SCOTT , FLOYD MICHAEL STEPHEN
IPC: G06F1/26
CPC classification number: G06F1/3296 , G06F1/3203 , G06F1/324 , Y02D10/126 , Y02D10/172
Abstract: PROBLEM TO BE SOLVED: To provide a managing operation associated with one or more voltage changes and one or more frequency changes. SOLUTION: A voltage change request and a frequency change request are associated with dynamic voltage and frequency scaling (DVFS) operations. The DVFS operation is transmitted by a processor to be executed by one or more direct current assemblies. A sequence associated with the one or more voltage changes and a sequence associated with the one or more frequency changes are detected by a system. The sequences are dynamically modified to enable insertion of an additional voltage change, whereby the additional voltage change indicates completion of one or more previous voltage change requests. Completion of the voltage change request enables one or more subsequent voltage change requests to be processed. When a voltage change request is not successfully completed, one or more future voltage changes are suspended. COPYRIGHT: (C)2011,JPO&INPIT
Abstract translation: 要解决的问题：提供与一个或多个电压变化和一个或多个频率变化相关联的管理操作。 解决方案：电压变化请求和频率变化请求与动态电压和频率缩放（DVFS）操作相关联。 DVFS操作由处理器发送以由一个或多个直流组件执行。 与一个或多个电压变化相关联的序列和与一个或多个频率变化相关联的序列由系统检测。 这些序列被动态地修改以允许插入额外的电压变化，由此额外的电压变化指示完成一个或多个先前的电压变化请求。 完成电压变化请求使得能够处理一个或多个后续电压变化请求。 当电压变化请求未成功完成时，将暂停一个或多个未来的电压变化。 版权所有（C）2011，JPO＆INPIT
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公开(公告)号：JP2002344420A
公开(公告)日：2002-11-29
申请号：JP2002078654
申请日：2002-03-20
Applicant: IBM
Inventor： DAVIS GORDON TAYLOR , DERBY JEFFREY HASKELL , ELEFTHERIOU EVANGELOS STAVROS , OELCER SEDAT , WARE MALCOLM SCOTT
Abstract: PROBLEM TO BE SOLVED: To reduce electric power demand of the line driver of a DSL server modem, by limiting the bandwidth of signals to be transmitted to a related client modem (namely, limiting power in signals), excluding the case where a client is intending data reception in a current physical frame (not in idle state). SOLUTION: A low-power DSL modem transmitter suited for incorporation into an integral DSLAM server line card transmits all the power physical frame, including a control channel and a data field when there are data to be transmitted, and transmits a physical frame having only the control channel or the control channel and a low-power synchronous field, when there are no data to be transmitted. By regulating the flow of data packets to the DSL selectively, a method for controlling total power consumed in the integral DSLAM is provided.
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公开(公告)号：CZ290716B6
公开(公告)日：2002-10-16
申请号：CZ54994
申请日：1992-08-26
Applicant: IBM , IBM DEUTSCHLAND
Inventor： CARMON DONALD EDWARD , CROUSE WILLIAM GEORGE , WARE MALCOLM SCOTT
Abstract: Disclosed is a multi-media user task (host) computer that is interfaced to a high-speed digital signal processor, which provides support functions to the host computer via an interprocessor bus master and direct memory access controller. Support of multiple dynamic hard real-time signal-processing task requirements are met by posting signal processor support task requests from the host processor through the interprocessor direct memory access controller to the signal processor and its operating system. The signal processor builds data transfer packet request execution lists in a partitioned queue in its own memory and executes internal signal processor tasks invoked by a user at the host system by extracting signal sample data from incoming data packets presented by the interprocessor direct memory access controller in response to its execution of the packet transfer request queues built by the signal processor in the partitioned queue. Processed signal values etc. are extracted from signal processor memory by the interprocessor direct memory access controller executing the partitioned packet request lists and delivered to the host processor. A very large number of packet transfers in support of numerous user tasks and implementing a very large number of direct memory access channels is thus made possible while avoiding the need for arbitration between the channels on the part of the signal processor or the host processor.
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Patent Agency Ranking
公开(公告)号：CZ9400549A3
公开(公告)日：2002-05-15
申请号：CZ54994
申请日：1992-08-26
Applicant: IBM , IBM DEUTSCHLAND
Inventor： CARMON DONALD EDWARD , CROUSE WILLIAM GEORGE , WARE MALCOLM SCOTT
Abstract: A multi-media user task (host) computer is interfaced to a high speed DSP which provides support functions to the host computer via an interprocessor DMA bus master and controller. Support of multiple dynamic hard real-time signal processing task requirements are met by posting signal processor support task requests from the host processor through the interprocessor DMA controller to the signal processor and its operating system. The signal processor builds data transfer packet request execution lists in a partitioned queue in its own memory and executes internal signal processor tasks invoked by users at the host system by extracting signal sample data from incoming data packets presented by the interprocessor DMA controller in response to its execution of the DMA packet transfer request queues built by the signal processor in the partitioned queue. Processed signal values etc. are extracted from signal processor memory by the DMA interprocessor controller executing the partitioned packet request lists and delivered to the host processor. A very large number of packet transfers in support of numerous user tasks and implementing a very large number of DMA channels is thus made possible while avoiding the need for arbitration between the channels on the part of the signal processor or the host processor.
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公开(公告)号：DE3784120D1
公开(公告)日：1993-03-25
申请号：DE3784120
申请日：1987-06-30
Applicant: IBM
Inventor： CROUSE WILLIAM GEORGE , WARE MALCOLM SCOTT
Abstract: Sub-band speech coders that depend on allocation of available bit capacity of a transmission medium to provide high quality speech coding for digital transmission are well known. The present invention utilizes one or more bit allocation tables to dynamically distribute the channel bit capacity bandwidth among the frequency bands according to the desired output quality of speech rather than by means of complex algorithms or simulation techniques. Multiple bit assignment tables are provided to allow various quality levels to be traded off as increasing bit rate demands are placed upon the transmission system. The technique is used for a single coder to achieve a minimum bit rate for a desired given level of subjective quality in speech output or may be used in a shared bit resource to maintain equal and minimum quality degradation for all users. The quality tables determine the number of bits to be dropped from the encoded representation of each signal sample to minimize the transmission load for a given coder without sacrificing speech quality to an unacceptable degree. Table entries are arranged based on the overall band peak energy level and on the sub-band peak energy distribution or spectrum as it is known in the field.
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公开(公告)号：DE69220169T2
公开(公告)日：1997-12-18
申请号：DE69220169
申请日：1992-08-28
Applicant: IBM
Inventor： MURRAY JACK THOMAS , UNGERBOECK GOTTFRIED , WARE MALCOLM SCOTT
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公开(公告)号：HU9400792D0
公开(公告)日：1994-07-28
申请号：HU9400792
申请日：1992-08-26
Applicant: IBM
Inventor： CROUSE WILLIAM GEORGE , CARMON DONALD EDWARD , WARE MALCOLM SCOTT
Abstract: A multi-media user task (host) computer is interfaced to a high speed DSP which provides support functions to the host computer via an interprocessor DMA bus master and controller. Support of multiple dynamic hard real-time signal processing task requirements are met by posting signal processor support task requests from the host processor through the interprocessor DMA controller to the signal processor and its operating system. The signal processor builds data transfer packet request execution lists in a partitioned queue in its own memory and executes internal signal processor tasks invoked by users at the host system by extracting signal sample data from incoming data packets presented by the interprocessor DMA controller in response to its execution of the DMA packet transfer request queues built by the signal processor in the partitioned queue. Processed signal values etc. are extracted from signal processor memory by the DMA interprocessor controller executing the partitioned packet request lists and delivered to the host processor. A very large number of packet transfers in support of numerous user tasks and implementing a very large number of DMA channels is thus made possible while avoiding the need for arbitration between the channels on the part of the signal processor or the host processor.
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