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    Multimedia computer system
    1.
    发明专利
    Multimedia computer system 未知

    公开(公告)号：CZ290716B6

    公开(公告)日：2002-10-16

    申请号：CZ54994

    申请日：1992-08-26

    Applicant: IBM ,  IBM DEUTSCHLAND

    Inventor： CARMON DONALD EDWARD ,  CROUSE WILLIAM GEORGE ,  WARE MALCOLM SCOTT

    IPC: G06F9/50 ,  G06F13/28 ,  G06F17/10 ,  G06F9/46

    Abstract: Disclosed is a multi-media user task (host) computer that is interfaced to a high-speed digital signal processor, which provides support functions to the host computer via an interprocessor bus master and direct memory access controller. Support of multiple dynamic hard real-time signal-processing task requirements are met by posting signal processor support task requests from the host processor through the interprocessor direct memory access controller to the signal processor and its operating system. The signal processor builds data transfer packet request execution lists in a partitioned queue in its own memory and executes internal signal processor tasks invoked by a user at the host system by extracting signal sample data from incoming data packets presented by the interprocessor direct memory access controller in response to its execution of the packet transfer request queues built by the signal processor in the partitioned queue. Processed signal values etc. are extracted from signal processor memory by the interprocessor direct memory access controller executing the partitioned packet request lists and delivered to the host processor. A very large number of packet transfers in support of numerous user tasks and implementing a very large number of direct memory access channels is thus made possible while avoiding the need for arbitration between the channels on the part of the signal processor or the host processor.

    Computer system having several media
    2.
    发明专利
    Computer system having several media 未知

    公开(公告)号：CZ9400549A3

    公开(公告)日：2002-05-15

    申请号：CZ54994

    申请日：1992-08-26

    Applicant: IBM ,  IBM DEUTSCHLAND

    Inventor： CARMON DONALD EDWARD ,  CROUSE WILLIAM GEORGE ,  WARE MALCOLM SCOTT

    IPC: G06F9/50 ,  G06F13/28 ,  G06F17/10 ,  G06F9/46

    Abstract: A multi-media user task (host) computer is interfaced to a high speed DSP which provides support functions to the host computer via an interprocessor DMA bus master and controller. Support of multiple dynamic hard real-time signal processing task requirements are met by posting signal processor support task requests from the host processor through the interprocessor DMA controller to the signal processor and its operating system. The signal processor builds data transfer packet request execution lists in a partitioned queue in its own memory and executes internal signal processor tasks invoked by users at the host system by extracting signal sample data from incoming data packets presented by the interprocessor DMA controller in response to its execution of the DMA packet transfer request queues built by the signal processor in the partitioned queue. Processed signal values etc. are extracted from signal processor memory by the DMA interprocessor controller executing the partitioned packet request lists and delivered to the host processor. A very large number of packet transfers in support of numerous user tasks and implementing a very large number of DMA channels is thus made possible while avoiding the need for arbitration between the channels on the part of the signal processor or the host processor.

    3.
    发明专利
    未知

    公开(公告)号：DE3784120D1

    公开(公告)日：1993-03-25

    申请号：DE3784120

    申请日：1987-06-30

    Applicant: IBM

    Inventor： CROUSE WILLIAM GEORGE ,  WARE MALCOLM SCOTT

    IPC: G10L19/02 ,  H04B1/66

    Abstract: Sub-band speech coders that depend on allocation of available bit capacity of a transmission medium to provide high quality speech coding for digital transmission are well known. The present invention utilizes one or more bit allocation tables to dynamically distribute the channel bit capacity bandwidth among the frequency bands according to the desired output quality of speech rather than by means of complex algorithms or simulation techniques. Multiple bit assignment tables are provided to allow various quality levels to be traded off as increasing bit rate demands are placed upon the transmission system. The technique is used for a single coder to achieve a minimum bit rate for a desired given level of subjective quality in speech output or may be used in a shared bit resource to maintain equal and minimum quality degradation for all users. The quality tables determine the number of bits to be dropped from the encoded representation of each signal sample to minimize the transmission load for a given coder without sacrificing speech quality to an unacceptable degree. Table entries are arranged based on the overall band peak energy level and on the sub-band peak energy distribution or spectrum as it is known in the field.

    5.
    发明专利
    未知

    公开(公告)号：DE1274638B

    公开(公告)日：1968-08-08

    申请号：DEJ0030612

    申请日：1966-04-14

    Applicant: IBM

    Inventor： CROUSE WILLIAM GEORGE

    IPC: H04B1/52 ,  H03B28/00 ,  H03F3/30 ,  H03G3/30 ,  H03G3/34 ,  H03G7/00 ,  H03G11/02 ,  H03K5/13 ,  H04L27/10 ,  H04L27/144 ,  H04L27/148 ,  H01L27/12

    Abstract: 1,137,710. Limiters. INTERNATIONAL BUSINESS MACHINES CORP. 12 April, 1966 [15 April, 1965], No. 15820/66. Heading H3T. A limiter comprises an amplifier with a semiconductor shunt negative feedback circuit whose impedance changes from a high to a low value when the input signal amplitude goes above a certain level, the feedback circuit comprising two oppositely poled semi-conductor devices in series with a capacitor, the whole being shunted by a resistor. Fig. 1 shows three such limiting stages in cascade, each stage having collector-base negative feedback through oppositely poled diodes 356, 357 operating on negative and positive going portions respectively of an input signal applied at 345. The diodes are preferably of the silicon type having a threshold above which their impedance falls. Negative noise peaks on the top of a positive-going signal will be substantially eliminated by the three stages (Fig. 3, not shown). The gain may be increased by using two amplifying transistors in each stage. The diodes may be replaced (Fig. 4, not shown) by the base-emitter paths of two saturated transistors of opposite conductivity types (see Specification, 1,054,908), or by two Zener diodes in series (Fig. 5, not shown). If an asymmetric output signal is acceptable only one Zener diode need be used, the non-limiting region lying between the forward and reverse breakdown points. The invention may be used in the frequency-shift data transmission system of Specification 1,137,705.

    MULTI-MEDIA SIGNAL PROCESSOR COMPUTER SYSTEM
    10.
    发明专利
    MULTI-MEDIA SIGNAL PROCESSOR COMPUTER SYSTEM 未知

    公开(公告)号：HU9400792D0

    公开(公告)日：1994-07-28

    申请号：HU9400792

    申请日：1992-08-26

    Applicant: IBM

    Inventor： CROUSE WILLIAM GEORGE ,  CARMON DONALD EDWARD ,  WARE MALCOLM SCOTT

    IPC: G06F9/50 ,  G06F13/28 ,  G06F17/10

    Abstract: A multi-media user task (host) computer is interfaced to a high speed DSP which provides support functions to the host computer via an interprocessor DMA bus master and controller. Support of multiple dynamic hard real-time signal processing task requirements are met by posting signal processor support task requests from the host processor through the interprocessor DMA controller to the signal processor and its operating system. The signal processor builds data transfer packet request execution lists in a partitioned queue in its own memory and executes internal signal processor tasks invoked by users at the host system by extracting signal sample data from incoming data packets presented by the interprocessor DMA controller in response to its execution of the DMA packet transfer request queues built by the signal processor in the partitioned queue. Processed signal values etc. are extracted from signal processor memory by the DMA interprocessor controller executing the partitioned packet request lists and delivered to the host processor. A very large number of packet transfers in support of numerous user tasks and implementing a very large number of DMA channels is thus made possible while avoiding the need for arbitration between the channels on the part of the signal processor or the host processor.

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