公开(公告)号：CZ290716B6

公开(公告)日：2002-10-16

申请号：CZ54994

申请日：1992-08-26

Applicant: IBM ,  IBM DEUTSCHLAND

Inventor： CARMON DONALD EDWARD ,  CROUSE WILLIAM GEORGE ,  WARE MALCOLM SCOTT

IPC: G06F9/50 ,  G06F13/28 ,  G06F17/10 ,  G06F9/46

Abstract: Disclosed is a multi-media user task (host) computer that is interfaced to a high-speed digital signal processor, which provides support functions to the host computer via an interprocessor bus master and direct memory access controller. Support of multiple dynamic hard real-time signal-processing task requirements are met by posting signal processor support task requests from the host processor through the interprocessor direct memory access controller to the signal processor and its operating system. The signal processor builds data transfer packet request execution lists in a partitioned queue in its own memory and executes internal signal processor tasks invoked by a user at the host system by extracting signal sample data from incoming data packets presented by the interprocessor direct memory access controller in response to its execution of the packet transfer request queues built by the signal processor in the partitioned queue. Processed signal values etc. are extracted from signal processor memory by the interprocessor direct memory access controller executing the partitioned packet request lists and delivered to the host processor. A very large number of packet transfers in support of numerous user tasks and implementing a very large number of direct memory access channels is thus made possible while avoiding the need for arbitration between the channels on the part of the signal processor or the host processor.

公开(公告)号：CZ9400549A3

公开(公告)日：2002-05-15

申请号：CZ54994

申请日：1992-08-26

Applicant: IBM ,  IBM DEUTSCHLAND

Inventor： CARMON DONALD EDWARD ,  CROUSE WILLIAM GEORGE ,  WARE MALCOLM SCOTT

IPC: G06F9/50 ,  G06F13/28 ,  G06F17/10 ,  G06F9/46

Abstract: A multi-media user task (host) computer is interfaced to a high speed DSP which provides support functions to the host computer via an interprocessor DMA bus master and controller. Support of multiple dynamic hard real-time signal processing task requirements are met by posting signal processor support task requests from the host processor through the interprocessor DMA controller to the signal processor and its operating system. The signal processor builds data transfer packet request execution lists in a partitioned queue in its own memory and executes internal signal processor tasks invoked by users at the host system by extracting signal sample data from incoming data packets presented by the interprocessor DMA controller in response to its execution of the DMA packet transfer request queues built by the signal processor in the partitioned queue. Processed signal values etc. are extracted from signal processor memory by the DMA interprocessor controller executing the partitioned packet request lists and delivered to the host processor. A very large number of packet transfers in support of numerous user tasks and implementing a very large number of DMA channels is thus made possible while avoiding the need for arbitration between the channels on the part of the signal processor or the host processor.

公开(公告)号：DE69224251T2

公开(公告)日：1998-08-13

申请号：DE69224251

申请日：1992-08-14

Applicant: IBM

Inventor： CARMON DONALD EDWARD

IPC: G06F9/46 ,  G06F11/00 ,  G06F11/34

Abstract: Hard, real-time, multi-tasking system is monitored by combined hardware and software and logic to detect overrun of any task beyond a declared maximum processor cycle limit for the task. Processor execution cycles utilized by DMA or interrupt processing and not related to the task being executed are not counted. Counter hardware and control logic reduces software overhead for monitoring execution cycle utilization by a task and provides capability not only of overrun detection, but programmed cycle usage alarm, consumed cycle count and overall processor loading or utilization measurements to be made.

公开(公告)号：DE69229909T2

公开(公告)日：2000-04-27

申请号：DE69229909

申请日：1992-12-22

Applicant: IBM

Inventor： CARMON DONALD EDWARD

IPC: G06F9/46 ,  G06F9/48

Abstract: An operating system for scheduling execution of a random set of periodically recurring hard, real-time tasks encountered in multi-media computer system applications and which is useful in a multi-tasking computer operating environment. Periodically recurring computer tasks having relatively short execution periods for which execution results are absolutely required in hard, real-time environments such as multi-media systems, create a significant task scheduling overhead reducing the available processor resource. Overhead processing at task invocation is eliminated in the invention by placing all active recurrent tasks in an execution queue, regardless of the task's current state of activity and by reprioritizing the order of execution of the tasks in the queue whenever a given task execution is completed. Measured by reduction in task scheduling overhead consumed by the processor in scheduling the tasks, this achieves a 50-100% improvement over conventional scheduling and operating systems.

公开(公告)号：DE69229909D1

公开(公告)日：1999-10-07

申请号：DE69229909

申请日：1992-12-22

Applicant: IBM

Inventor： CARMON DONALD EDWARD

IPC: G06F9/46 ,  G06F9/48

Abstract: An operating system for scheduling execution of a random set of periodically recurring hard, real-time tasks encountered in multi-media computer system applications and which is useful in a multi-tasking computer operating environment. Periodically recurring computer tasks having relatively short execution periods for which execution results are absolutely required in hard, real-time environments such as multi-media systems, create a significant task scheduling overhead reducing the available processor resource. Overhead processing at task invocation is eliminated in the invention by placing all active recurrent tasks in an execution queue, regardless of the task's current state of activity and by reprioritizing the order of execution of the tasks in the queue whenever a given task execution is completed. Measured by reduction in task scheduling overhead consumed by the processor in scheduling the tasks, this achieves a 50-100% improvement over conventional scheduling and operating systems.

公开(公告)号：HU219533B

公开(公告)日：2001-05-28

申请号：HU9400792

申请日：1992-08-26

Applicant: IBM

Inventor： CARMON DONALD EDWARD ,  CROUSE WILLIAM GEORGE ,  WARE MALCOLM SCOTT

IPC: G06F9/50 ,  G06F13/28 ,  G06F17/10

Abstract: A multi-media user task (host) computer is interfaced to a high speed DSP which provides support functions to the host computer via an interprocessor DMA bus master and controller. Support of multiple dynamic hard real-time signal processing task requirements are met by posting signal processor support task requests from the host processor through the interprocessor DMA controller to the signal processor and its operating system. The signal processor builds data transfer packet request execution lists in a partitioned queue in its own memory and executes internal signal processor tasks invoked by users at the host system by extracting signal sample data from incoming data packets presented by the interprocessor DMA controller in response to its execution of the DMA packet transfer request queues built by the signal processor in the partitioned queue. Processed signal values etc. are extracted from signal processor memory by the DMA interprocessor controller executing the partitioned packet request lists and delivered to the host processor. A very large number of packet transfers in support of numerous user tasks and implementing a very large number of DMA channels is thus made possible while avoiding the need for arbitration between the channels on the part of the signal processor or the host processor.

公开(公告)号：AT149259T

公开(公告)日：1997-03-15

申请号：AT92918307

申请日：1992-08-26

Applicant: IBM

Inventor： CARMON DONALD EDWARD ,  CROUSE WILLIAM GEORGE ,  WARE MALCOLM SCOTT

IPC: G06F9/50 ,  G06F13/28 ,  G06F17/10 ,  G06F9/46

Abstract: A multi-media user task (host) computer is interfaced to a high speed DSP which provides support functions to the host computer via an interprocessor DMA bus master and controller. Support of multiple dynamic hard real-time signal processing task requirements are met by posting signal processor support task requests from the host processor through the interprocessor DMA controller to the signal processor and its operating system. The signal processor builds data transfer packet request execution lists in a partitioned queue in its own memory and executes internal signal processor tasks invoked by users at the host system by extracting signal sample data from incoming data packets presented by the interprocessor DMA controller in response to its execution of the DMA packet transfer request queues built by the signal processor in the partitioned queue. Processed signal values etc. are extracted from signal processor memory by the DMA interprocessor controller executing the partitioned packet request lists and delivered to the host processor. A very large number of packet transfers in support of numerous user tasks and implementing a very large number of DMA channels is thus made possible while avoiding the need for arbitration between the channels on the part of the signal processor or the host processor.

公开(公告)号：HUT68084A

公开(公告)日：1995-05-29

申请号：HU9400792

申请日：1992-08-26

Applicant: IBM

Inventor： CROUSE WILLIAM GEORGE ,  CARMON DONALD EDWARD ,  WARE MALCOLM SCOTT

IPC: G06F9/50 ,  G06F13/28 ,  G06F17/10

Abstract: A multi-media user task (host) computer is interfaced to a high speed DSP which provides support functions to the host computer via an interprocessor DMA bus master and controller. Support of multiple dynamic hard real-time signal processing task requirements are met by posting signal processor support task requests from the host processor through the interprocessor DMA controller to the signal processor and its operating system. The signal processor builds data transfer packet request execution lists in a partitioned queue in its own memory and executes internal signal processor tasks invoked by users at the host system by extracting signal sample data from incoming data packets presented by the interprocessor DMA controller in response to its execution of the DMA packet transfer request queues built by the signal processor in the partitioned queue. Processed signal values etc. are extracted from signal processor memory by the DMA interprocessor controller executing the partitioned packet request lists and delivered to the host processor. A very large number of packet transfers in support of numerous user tasks and implementing a very large number of DMA channels is thus made possible while avoiding the need for arbitration between the channels on the part of the signal processor or the host processor.

公开(公告)号：AT184119T

公开(公告)日：1999-09-15

申请号：AT92480201

申请日：1992-12-22

Applicant: IBM

Inventor： CARMON DONALD EDWARD

IPC: G06F9/46 ,  G06F9/48

Abstract: An operating system for scheduling execution of a random set of periodically recurring hard, real-time tasks encountered in multi-media computer system applications and which is useful in a multi-tasking computer operating environment. Periodically recurring computer tasks having relatively short execution periods for which execution results are absolutely required in hard, real-time environments such as multi-media systems, create a significant task scheduling overhead reducing the available processor resource. Overhead processing at task invocation is eliminated in the invention by placing all active recurrent tasks in an execution queue, regardless of the task's current state of activity and by reprioritizing the order of execution of the tasks in the queue whenever a given task execution is completed. Measured by reduction in task scheduling overhead consumed by the processor in scheduling the tasks, this achieves a 50-100% improvement over conventional scheduling and operating systems.

公开(公告)号：DE69224251D1

公开(公告)日：1998-03-05

申请号：DE69224251

申请日：1992-08-14

Applicant: IBM

Inventor： CARMON DONALD EDWARD

IPC: G06F9/46 ,  G06F11/00 ,  G06F11/34

Abstract: Hard, real-time, multi-tasking system is monitored by combined hardware and software and logic to detect overrun of any task beyond a declared maximum processor cycle limit for the task. Processor execution cycles utilized by DMA or interrupt processing and not related to the task being executed are not counted. Counter hardware and control logic reduces software overhead for monitoring execution cycle utilization by a task and provides capability not only of overrun detection, but programmed cycle usage alarm, consumed cycle count and overall processor loading or utilization measurements to be made.