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    Security architecture for system-on-chip
    11.
    发明专利
    Security architecture for system-on-chip 有权
    系统级芯片的安全架构

    公开(公告)号：JP2005018770A

    公开(公告)日：2005-01-20

    申请号：JP2004184034

    申请日：2004-06-22

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： CRAFT DAVID JOHN ,  DAY MICHAEL NORMAN ,  HOFSTEE HARM PETER ,  JOHNS CHARLES RAY ,  LIBERTY JOHN SAMUEL

    IPC: G06F12/14 ,  G06F21/22 ,  G06F21/24 ,  G09C1/00 ,  H04L9/08 ,  G06F1/00

    CPC classification number: G06F21/53 ,  H04L9/3226 ,  H04L2209/56

    Abstract: PROBLEM TO BE SOLVED: To provide authentication of either code or data or both, and protected execution environments. SOLUTION: For authentication of code or data, a local storage is dynamically divided and division cancelled. The local storage is divided into an isolated section and a non-isolated section. The code or the data are loaded in the isolated section. Either the code or the data are authenticated in the isolated section of the local storage. After the authentication, the code is executed. After the execution, a memory within the isolated section of an attached processor unit, and the attached processor unit performs division cancellation with the isolated section within the local storage. COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：提供代码或数据或两者的认证，以及受保护的执行环境。

    解决方案：对于代码或数据的验证，本地存储器被动态划分并分割。 本地存储分为隔离区段和非隔离区段。 代码或数据被加载到隔离的部分。 代码或数据在本地存储的隔离部分进行身份验证。 认证后，执行代码。 在执行之后，附接的处理器单元的隔离部分内的存储器，以及所附加的处理器单元使用本地存储器内的隔离部分进行分离消除。 版权所有（C）2005，JPO＆NCIPI

    METHOD FOR INTEGRATING MULTIPLE OBJECT FILES FROM HETEROGENEOUS ARCHITECTURES INTO A SET OF FILES
    13.
    发明申请
    METHOD FOR INTEGRATING MULTIPLE OBJECT FILES FROM HETEROGENEOUS ARCHITECTURES INTO A SET OF FILES 审中-公开
    将多个异构体结构中的多个对象文件整合到一组文件中的方法

    公开(公告)号：WO2006049740A3

    公开(公告)日：2006-08-10

    申请号：PCT/US2005034460

    申请日：2005-09-23

    Applicant: SONY COMPUTER ENTERTAINMENT INC ,  IBM ,  TOSHIBA KK

    Inventor： CHOW ALEX CHUNGHEN ,  DAY MICHAEL NORMAN ,  GOWEN MICHAEL STAN ,  INOUE KEISUKE ,  XENIDIS JAMES ,  UCHIKAWA TAKAYUKI

    IPC: G06F9/445

    CPC classification number: G06F8/54 ,  G06F9/4425

    Abstract: The present invention is a method for integrating multiple object codes from heterogeneous architectures. For a program on a first processor to reference a program from the name space of a second processor, the object code for the second-processor program is enclosed in a wrapper to create object code in the first-processor name space. The header of the wrapped object code defines a new symbol in the name space of the first processor, and the symbol points to the second-processor object code contained in the wrapped object code. Instead of directly referencing the second-processor object code, the referencing program on the first processor references the wrapped object code. A system tool can be used to wrap the object code which runs on the second processor.

    Abstract translation: 本发明是用于集成来自异构体系结构的多个目标代码的方法。 对于第一个处理器上的程序从第二个处理器的名称空间引用程序，第二个处理器程序的目标代码封装在包装器中，以在第一个处理器名称空间中创建目标代码。 包装目标代码的头文件在第一个处理器的名称空间中定义一个新符号，该符号指向包含在包装目标代码中的第二个处理器目标代码。 第一处理器上的引用程序不是直接引用第二处理器对象代码，而是引用包装的对象代码。 系统工具可以用来包装在第二个处理器上运行的目标代码。

    14.
    发明专利
    未知

    公开(公告)号：DE602005009494D1

    公开(公告)日：2008-10-16

    申请号：DE602005009494

    申请日：2005-07-06

    Applicant: SONY COMPUTER ENTERTAINMENT INC ,  IBM

    Inventor： DAY MICHAEL NORMAN ,  JOHNS CHARLES RAY ,  LIU PEICHUN PETER ,  TRUONG THUONG QUANG ,  YAMAZAKI TAKESHI

    IPC: G06F13/28

    Abstract: A method, an apparatus, and a computer program are provided for controlling memory access. Direct Memory Access (DMA) units have become commonplace in a number of bus architectures. However, managing limited system resources has become a challenge with multiple DMA units. In order to mange the multitude of commands generated and preserve dependencies, embedded flags in commands or a barrier command are used. These operations then can control the order in which commands are executed so as to preserve dependencies.

    SYSTEM AND METHOD FOR VIRTUALIZATION OF PROCESSOR RESOURCES
    15.
    发明专利
    SYSTEM AND METHOD FOR VIRTUALIZATION OF PROCESSOR RESOURCES 未知

    公开(公告)号：CA2577865A1

    公开(公告)日：2006-04-06

    申请号：CA2577865

    申请日：2005-08-24

    Applicant: IBM

    Inventor： NUTTER MARK RICHARD ,  DAY MICHAEL NORMAN ,  AGUILAR MAXIMINO JR ,  XENIDIS JAMES

    IPC: G06F12/10 ,  G06F12/02

    Abstract: A system and method for virtualization of processor resources is presented. A thread is created on a processor and the processor's local memory is mapped into an effective address space. In doing so, the processor's local memory is accessible by other processors, regardless of whether the processor is running. Additional threads create additional local memory mappings into the effective address space. The effective address space corresponds to either a physical local memory or a "soft" copy area. When the processor is running, a different processor may access data that is located in the first processor's local memory from the processor's local storage area. When the processor is not running, a softcopy of the processor's local memory is stored in a memory location (i.e. locked cache memory, pinned system memory, virtual memory, etc.) for other processors to continue accessing.

    Diskette facilitated preloading of system from CD ROM
    17.
    发明专利
    Diskette facilitated preloading of system from CD ROM 未知

    公开(公告)号：GB2309104A

    公开(公告)日：1997-07-16

    申请号：GB9600534

    申请日：1996-01-11

    Applicant: IBM

    Inventor： SIMPSON PHILIP MCARTHUR ,  SEEN AYLWIN YIM ,  DAY MICHAEL NORMAN ,  FRYE JESSE CHARLES

    IPC: G06F9/445

    Abstract: A manufacturing compact disk is provided which stores the complete range of software which may be stored on the computer system. Associated with the computer system is a manufacturing diskette which includes installation files which define which software on the CD is to be transferred to the system. This manufacturing diskette also includes diagnostic and/or other code which is employed at other stages of the system assembly process.

    20.
    发明专利
    未知

    公开(公告)号：BR8606400A

    公开(公告)日：1987-10-13

    申请号：BR8606400

    申请日：1986-12-23

    Applicant: IBM

    Inventor： DAY MICHAEL NORMAN

    IPC: G06F1/04 ,  G06F1/32 ,  G06F15/02 ,  G06F13/14

    Abstract: An apparatus and method are provided for disabling the clocking of a processor in a battery operated computer during non-processing times. The clocking is disabled at the conclusion of a processing operation. The clocking can then be re-enabled using interrupts from any one of a plurality of sources, such as an I/O device or a direct memory access. Application programs and operating system programs running on the system can specify the stopping of the system clock and the central processor until a specified event which had been requested occurs, or until an optional time-out period has expired. In this situation, the event is defined as one that results in either a system interrupt from an I/O device or from a direct memory access operation. The stopping of the system clock is a two part operation wherein in the first part the stopping mechanism is first armed. If an interrupt is received subsequent to arming, then it will be processed and the arming mechanism will be reset. However, if an interrupt does not occur after arming within a specified time period, then the system clock will be stopped.

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