公开(公告)号：AU2145983A

公开(公告)日：1984-07-05

申请号：AU2145983

申请日：1983-11-17

Applicant: IBM

Inventor： BOISSEAU MARC ,  BORIE JEAN CLAUDE ,  CROISIER ALAIN ,  DEMANGE MICHEL ,  LEBIZAY GERALD ,  ROSSI JEAN-PIERRE PHILLIPPE

IPC: H04Q11/04 ,  H04Q11/06 ,  H04L5/22 ,  H04L11/20

公开(公告)号：CH600438A5

公开(公告)日：1978-06-15

申请号：CH1539775

申请日：1975-11-27

Applicant: IBM

Inventor： BORIE JEAN-CLAUDE ,  COUDER ALAIN ,  DAUBY ALAIN ,  DEMANGE MICHEL ,  LEBIZAY GERALD ,  LECHACZINSKY MICHEL

IPC: H04Q3/545 ,  G06F1/02 ,  G06F9/46 ,  G06F13/36 ,  G06F13/40 ,  G06F15/80 ,  G06F17/10 ,  H04Q11/04 ,  G06F15/00 ,  G06F15/20

Abstract: A modular digital signal processor based on a master-slave architecture has the capability of expanding its processing power by aggregating additional modules in a tree type structure. In such a processor the control functions are subdivided into groups, each for performance in a distinct control unit. One or more of the control units can perform a master function with respect to one or several slaved control units and can itself be a slave to a higher level control unit. The arithmetic data functions of the processor are performed in pipe line multiplier-accumulator units (PMAU), each of which is controlled by, instructions from an associated control unit.