公开(公告)号：US3902055A

公开(公告)日：1975-08-26

申请号：US44913374

申请日：1974-03-07

Applicant: IBM

Inventor： HAIMS MURRAY J ,  HAO HSIEH T ,  LEBIZAY GERALD ,  WEISS ALFRED

IPC: G06F7/501 ,  G06F7/50 ,  G06F7/503 ,  G06F7/506

CPC classification number: G06F7/506 ,  G06F7/501

Abstract: An improvement in binary adder circuits based on a new Boolean algorithm is disclosed. The arrangement permits calculation of the carry from the logical combination of the addend, the EXCLUSIVE OR of the addend and the augend, and the carry of the next preceding stage. The circuit is readily implemented in NOR logic and has particular application in large scale integrated circuits (LSI).

公开(公告)号：DE3277054D1

公开(公告)日：1987-09-24

申请号：DE3277054

申请日：1982-12-28

Applicant: IBM ,  IBM FRANCE

Inventor： BOISSEAU MARC ,  BORIE JEAN CLAUDE ,  CROISIER ALAIN ,  DEMANGE MICHEL ,  LEBIZAY GERALD ,  ROSSI JEAN-PIERRE PHILIPPE

IPC: H04Q11/04 ,  H04Q11/06

公开(公告)号：DE2743765A1

公开(公告)日：1978-04-06

申请号：DE2743765

申请日：1977-09-29

Applicant: IBM

Inventor： CROISIER ALAIN ,  LEBIZAY GERALD ,  JEAN PHILIPPE ANDRE

IPC: H04M3/00 ,  H04Q3/00 ,  H04Q3/42 ,  H04Q3/47

公开(公告)号：FR2328349A1

公开(公告)日：1977-05-13

申请号：FR7308009

申请日：1973-03-01

Applicant: IBM FRANCE

Inventor： LEBIZAY GERALD ,  COUDER ALAIN

IPC: G06F13/00 ,  H04Q11/04 ,  H04J3/08 ,  H04L5/14

Abstract: Two-way links communication capability between time-division multiplexed subsystems is provided via dual time division address and data busses correlated by a recirculating memory having sections respectively associated with the address busses. Addresses on the address busses are recognized by the individual subsystems and further decoded to gate data to and from the busses data according to time slots assigned to terminal devices in the subsystems. The dual bus arrangement provides a full-duplex link in the sense that there is simultaneous communication via the two data busses, one each way.

公开(公告)号：FR2312072A1

公开(公告)日：1976-12-17

申请号：FR7516536

申请日：1975-05-21

Applicant: IBM

Inventor： KERRIGAN MICHAEL ,  LEBIZAY GERALD ,  SORLEY OLIN LOWE MAC ,  WEISS ALFRED

IPC: G06F13/36 ,  G06F13/34 ,  G06F13/00

Abstract: An input-output port control subsystem for use with a computer system having separate source and destination buses incorporated therein. Said system including circuitry for controlling operations of said system and said input/output subsystem, said subsystem including a bidirectional input/output bus for transferring data to and from said system, and separate gating means for selectively connecting said source and destination buses to said bidirectional I/O bus. External devices are connected to said bus thru an adaptor unit which is directly connected to said processing system by appropriate control lines. The input/output subsystem is adapted to operate either under programmed I/O control mode thru the central processing system or in cycle steal mode wherein the I/O devices themselves request cycle steal service time on the I/O bus thru their connected adaptor.

公开(公告)号：DE69330675T2

公开(公告)日：2002-06-13

申请号：DE69330675

申请日：1993-06-03

Applicant: IBM

Inventor： GALAND CLAUDE ,  LEBIZAY GERALD

IPC: G06F13/00 ,  H04L29/06

Abstract: A packet switching communication system is improved by using a packet header structure which does not require a fixed format. The packet header comprises a chain of 2 byte command/data segments. Each command/data segment contains generic bits and a routing field. One of the generic bits (bit 1) allows the header to be extended with another command/data segment.

公开(公告)号：DE69330675D1

公开(公告)日：2001-10-04

申请号：DE69330675

申请日：1993-06-03

Applicant: IBM

Inventor： GALAND CLAUDE ,  LEBIZAY GERALD

IPC: G06F13/00 ,  H04L29/06

Abstract: A packet switching communication system is improved by using a packet header structure which does not require a fixed format. The packet header comprises a chain of 2 byte command/data segments. Each command/data segment contains generic bits and a routing field. One of the generic bits (bit 1) allows the header to be extended with another command/data segment.

公开(公告)号：DE69305734T2

公开(公告)日：1997-05-15

申请号：DE69305734

申请日：1993-06-30

Applicant: IBM

Inventor： GALAND CLAUDE ,  MAUDUIT DANIEL ,  PAUPORTE ANDRE ,  SPAGNOL VICTOR ,  LEBIZAY GERALD ,  MUNIER JEAN-MARIE ,  SAINT-GEORGES ERIC

IPC: H04L29/06

Abstract: A high performance data packet buffering method and a programmable data communication adapter for high speed packet transmission networks are disclosed. The line adapter includes programmable processing means, for receiving and transmitting data packets of fixed or variable length. This system is characterized in that it comprises means for buffering (132) said data packets, means for identifying said buffering means and said data packets in said buffering means, means for queueing (Figure 15) in storing means (131) said identifying means in a single instruction, means for dequeueing (Figure 16) from said storing (131) means said identifying means in another single instruction , means for releasing said buffering means, Each instruction comprises up to three operations executed in parallel by said processing means : an arithmetical and logical (ALU) operation on said identifying means, a memory operation on said storing means, and a sequence operation.

公开(公告)号：DE69305734D1

公开(公告)日：1996-12-05

申请号：DE69305734

申请日：1993-06-30

Applicant: IBM

Inventor： GALAND CLAUDE ,  MAUDUIT DANIEL ,  PAUPORTE ANDRE ,  SPAGNOL VICTOR ,  LEBIZAY GERALD ,  MUNIER JEAN-MARIE ,  SAINT-GEORGES ERIC

IPC: H04L29/06

Abstract: A high performance data packet buffering method and a programmable data communication adapter for high speed packet transmission networks are disclosed. The line adapter includes programmable processing means, for receiving and transmitting data packets of fixed or variable length. This system is characterized in that it comprises means for buffering (132) said data packets, means for identifying said buffering means and said data packets in said buffering means, means for queueing (Figure 15) in storing means (131) said identifying means in a single instruction, means for dequeueing (Figure 16) from said storing (131) means said identifying means in another single instruction , means for releasing said buffering means, Each instruction comprises up to three operations executed in parallel by said processing means : an arithmetical and logical (ALU) operation on said identifying means, a memory operation on said storing means, and a sequence operation.

公开(公告)号：CA2144402A1

公开(公告)日：1995-10-15

申请号：CA2144402

申请日：1995-03-10

Applicant: IBM

Inventor： LEBIZAY GERALD ,  MUNIER JEAN M ,  PAUPORTE ANDRE ,  SPAGNOL VICTOR

IPC: H04L12/56

Abstract: The present invention relates to an efficient point-to-point and multi-points routing system and method for programmable data communication adapters in packetswitching nodes of high speed networks. The general principles of this efficiency are as follows. First, data packets are never copied, only packet pointers are copied for each destination, Space in Buffer Memory is saved, the number of instructions is significantly reduced improving the packet throughput (number of packets per seconds that the adapter is able to transmit). and the routing is independent of the packets length. Second, no overhead is generated by the multi-points mechanism in the real time procedures, the underrun/overrun problems on the outputs are reduced and the efficiency of the adapter in term data throughput (bits per second) is significantly improved. Third, each output is processed independently by means of interrupts, lines are managed in real time and lines of different speed or protocol can be supported in parallel. Fourth, the release of the resources is entirely realized on a non priority mode.