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    SYNCHRONIZING SYSTEM FOR A MULTIPLEXED LOOP COMMUNICATION NETWORK
    2.
    发明专利
    SYNCHRONIZING SYSTEM FOR A MULTIPLEXED LOOP COMMUNICATION NETWORK 未知

    公开(公告)号：DE3275692D1

    公开(公告)日：1987-04-16

    申请号：DE3275692

    申请日：1982-12-28

    Applicant: IBM ,  IBM FRANCE

    Inventor： AMBOISE MODESTE ,  DEMANGE MICHEL ,  LEBIZAY GERARD ,  MUNIER JEAN-MARIE ,  PEYRONNENC MICHEL HENRI PAUL

    IPC: H04L5/22 ,  H04J3/06 ,  H04L12/42 ,  H04Q11/04 ,  H04L11/16 ,  H04L7/00

    Abstract: The contents of input time-division channels on a closed-loop link (10LO, 10HI) are stored in a memory (173) at the address supplied by an input address counter (IAC) controlled by an incoming timing signal (2MCR). The memory is read out under control of an output address counter (OAC) controlled by an outgoing timing signal (2MCT). Each time interval is divided into one read period and two write periods. Means (186) are provided to select one of the two write periods dependent on the phase relationship between the incoming and outgoing timing signals. The units connected in series by means of the closed-loop link receive a timing signal circulating on a timing loop (15) that is closed by a master timing device (13). Slave timing devices (18) inserted in the timing loop regenerate the timing signals circulating thereon and check same.

    3.
    发明专利
    未知

    公开(公告)号：DE68918275T2

    公开(公告)日：1995-03-30

    申请号：DE68918275

    申请日：1989-06-29

    Applicant: IBM

    Inventor： LEBIZAY GERALD ,  DEMANGE MICHEL ,  VEDRENNE ALAIN ,  MILEWSKI ANDRZEJ

    IPC: H04Q3/00 ,  H04L12/56

    Abstract: A 3-stage switching system is provided for generating, i.e. finding, reserving and setting, path from one switch entrance port (1) to at least one switch exit port (transmit side) for asynchronously received and buffered data cells. While an Nth cell is being transferred, control means (36) generate a control word including the switch exit port address for cell (N+1)th to be subsequently transferred. Said control word is used to find and reserve a path through the switch on a stage-by-stage basis, and then set said path, if any, using a fed back acknowledgement. The (N+1)th cell path generation is performed during cell N transfer, on a cycle stealing basis.

    TIME-SPACE-TIME SWITCHING NETWORK USING A CLOSED-LOOP LINK
    7.
    发明专利
    TIME-SPACE-TIME SWITCHING NETWORK USING A CLOSED-LOOP LINK 未知

    公开(公告)号：CA1210841A

    公开(公告)日：1986-09-02

    申请号：CA440704

    申请日：1983-11-08

    Applicant: IBM

    Inventor： BOISSEAU MARC ,  BORIE JEAN C ,  CROISIER ALAIN ,  DEMANGE MICHEL ,  LEBIZAY GERALD ,  ROSSI JEAN-PIERRE P

    IPC: H04Q11/04 ,  H04Q11/06

    Abstract: A TIME-SPACE-TIME SWITCHING NETWORK USING A CLOSED-LOOP LINK A switching network for selectively connecting at least one input time-division channel on an input link (IL) to at least one output time-division channel on an output link (OL). The network is organized around a closed-loop link on which circulates a multiplex message carrying 512 time-division exchange channels. The input and output links are respectively multiplexed onto an input multiplex link (IML) and an output multiplex link (OML) which are coupled to the closed loop by a switching module (SM). Each switching module comprises an input buffer (IB), an output buffer (OB) and a local buffer (LB) the addressing of which is selectively controlled by a time slot counter (CTR) or a corresponding pointer memory. So-called "broadcast" connections coupling one input channel to several output channels, and "in-cast" connections coupling several input channels to one output channel, can be established. Each of these connections uses only one exchange channel.

    10.
    发明专利
    未知

    公开(公告)号：DE68918275D1

    公开(公告)日：1994-10-20

    申请号：DE68918275

    申请日：1989-06-29

    Applicant: IBM

    Inventor： LEBIZAY GERALD ,  DEMANGE MICHEL ,  VEDRENNE ALAIN ,  MILEWSKI ANDRZEJ

    IPC: H04Q3/00 ,  H04L12/56

    Abstract: A 3-stage switching system is provided for generating, i.e. finding, reserving and setting, path from one switch entrance port (1) to at least one switch exit port (transmit side) for asynchronously received and buffered data cells. While an Nth cell is being transferred, control means (36) generate a control word including the switch exit port address for cell (N+1)th to be subsequently transferred. Said control word is used to find and reserve a path through the switch on a stage-by-stage basis, and then set said path, if any, using a fed back acknowledgement. The (N+1)th cell path generation is performed during cell N transfer, on a cycle stealing basis.

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