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    Gate controlled diode memory cells
    11.
    发明专利
    Gate controlled diode memory cells 有权
    门控二极管记忆体

    公开(公告)号：JP2005175494A

    公开(公告)日：2005-06-30

    申请号：JP2004357562

    申请日：2004-12-10

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： LUK WING K ,  DENNARD ROBERT H

    IPC: H01L27/108 ,  G11C11/36 ,  G11C11/401 ,  G11C11/405 ,  G11C11/409 ,  H01L21/8242

    CPC classification number: G11C11/405

    Abstract: PROBLEM TO BE SOLVED: To provide gate controlled diode memory cells having charging capability. SOLUTION: The gate controlled diode memory cell includes one or more transistors, such as field effect transistors ("FETs"), and a gate controlled diode in signal communication with the FETs, and the gate of the gate controlled diode is in signal communication with the source of a first FET, wherein the gate of the gate controlled diode forms one terminal of the storage cell and the source of the gate controlled diode forms another terminal of the storage cell, the drain of the first FET being in signal communication with a bitline ("BL") and the gate of the first FET being in signal communication with a write wordline ("WLw"), and the source of the gate controlled diode being in signal communication with a read wordline ("WLr"). COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：提供具有充电能力的栅极控制二极管存储单元。 解决方案：栅极控制二极管存储单元包括一个或多个晶体管，例如场效应晶体管（“FET”）以及与FET信号通信的栅极控制二极管，并且栅极控制二极管的栅极处于 与第一FET的源极进行信号通信，其中栅极控制二极管的栅极形成存储单元的一个端子，并且栅极控制二极管的源极形成存储单元的另一个端子，第一FET的漏极处于信号 与位线（“BL”）的通信，并且第一FET的栅极与写入字线（“WLw”）进行信号通信，并且栅极控制二极管的源极与读取字线（“WLr”）进行信号通信， ）。 版权所有（C）2005，JPO＆NCIPI

    Silicon on insulator latch up pulse radiation detector
    13.
    发明专利
    Silicon on insulator latch up pulse radiation detector 有权
    绝缘子上的硅绝缘脉冲辐射探测器

    公开(公告)号：JP2006013114A

    公开(公告)日：2006-01-12

    申请号：JP2004187616

    申请日：2004-06-25

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： COTTRELL PETER E ,  DENNARD ROBERT H ,  EDWARD J NOWAKU ,  ROHRER NORMAN J

    IPC: H01L27/14 ,  G01T1/24 ,  H01L29/74 ,  H01L29/786 ,  H01L31/09

    Abstract: PROBLEM TO BE SOLVED: To provide a radiation detector formed by using a silicon-on insulator technology.
    SOLUTION: The radiation detector comprises a silicon layer formed on an insulating substrate and having a PNPN structure, and a gate layer formed on the PNPN structure and having a PN gate. Latch-up occurs only in response to incident radiation in the radiation detector. In a second mode, the radiation detector has a silicon-on insulator PNPN diode structure and latch-up occurs only in response to incident radiation in the radiation detector. In a third mode, a silicon-on insulator radiation detector has a silicon layer formed on the insulating substrate, the silicon layer has the PNPN structure and a gate layer formed thereon, the gate layer has a PN gate, and latch-up occurs only in response to incident radiation in the radiation detector.
    COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：提供通过使用硅绝缘体技术形成的辐射检测器。 解决方案：辐射检测器包括形成在绝缘衬底上并具有PNPN结构的硅层和形成在PNPN结构上并具有PN栅极的栅极层。 仅在响应于辐射探测器中的入射辐射时发生闩锁。 在第二种模式中，辐射探测器具有硅上绝缘体PNPN二极管结构，并且只在响应于辐射探测器中的入射辐射而发生闩锁。 在第三种模式中，硅绝缘体辐射探测器具有形成在绝缘衬底上的硅层，硅层具有PNPN结构和形成于其上的栅极层，栅极层具有PN栅极，并且仅闩锁发生 响应辐射检测器中的入射辐射。 版权所有（C）2006，JPO＆NCIPI

    15.
    发明专利
    未知

    公开(公告)号：FR2351502A1

    公开(公告)日：1977-12-09

    申请号：FR7710334

    申请日：1977-03-30

    Applicant: IBM

    Inventor： DENNARD ROBERT H ,  RIDEOUT VINCENT L

    IPC: H01L27/10 ,  H01L21/28 ,  H01L21/316 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L21/31 ,  H01L27/04

    Abstract: A field effect transistor (FET) with a unique gate structure is disclosed wherein the polycrystalline silicon (polysilicon) gate is self-aligned on its ends with respect to the conductive source and drain regions, and is self-aligned on its sides with respect to the nonconductive field isolation regions. The boundaries of these conductive and nonconductive regions determine the boundaries of the channel region of the FET. This double self-alignment feature results in a polysilicon gate, the lateral dimensions and location of which correlate directly with the lateral dimensions and location of the channel region of the FET. The unique gate fabrication technique employed according to the present invention comprises delineating lithographic patterns twice in the same polysilicon layer using the same oxidation barrier masking layer; whereby the first lithographic pattern delineates the FET device regions, and the next lithographic pattern forms the gate regions wherever the two patterns cross each other (i.e., wherever they delineate a common area).

    SELF-REGISTERING METHOD OF FABRICATING FIELD EFFECT TRANSISTORS
    17.
    发明专利
    SELF-REGISTERING METHOD OF FABRICATING FIELD EFFECT TRANSISTORS 未知

    公开(公告)号：CA1078077A

    公开(公告)日：1980-05-20

    申请号：CA279093

    申请日：1977-05-25

    Applicant: IBM

    Inventor： DENNARD ROBERT H ,  RIDEOUT VINCENT L

    IPC: H01L27/088 ,  H01L21/265 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/52 ,  H01L29/417 ,  H01L29/78 ,  H01L27/10 ,  H01L29/76

    Abstract: SELF-REGISTERING METHOD OF FABRICATING FIELD EFFECT TRANSISTORS A method of fabricating a field effect transistor (FET) wherein a self-registered or misregistration tolerant electrical connection is provided between the gate electrode and a metallic interconnection line. The method involves a unique structure which includes a thick deposited oxide insulation layer and an etch stopping layer over doped silicon source and drain regions, over polysilicon gate electrode regions, and over field isolation regions. The etch stopping layer facilitates fabrication of a selfregistering electrical connection between the gate electrode and a metallic interconnection line wherever desired. The thick deposited oxide layer provides reduced capacitive coupling between the insulated regions and the metallic interconnection line when compared to known self-registered gate contacting methods that employ only thermally grown oxide insulation. The method also includes the provision for controlling the removal of insulation over the gate electrode wherever desired without seriously degrading the insulation over other parts of the structure. The disclosed method further relates to fabricating an integrated circuit containing FETs having a self-registered electrical connection between the gate electrode and the metallic interconnection line, the gate electrode self-aligned with respect to the source and drain regions, and wherein FETs of the integrated circuit have: a channel region; a gate insulator; an electrically conductive gate electrode; source and drain regions; thick insulation over the source and drain and over the gate electrode except in the contact areas; field isolation or field shield regions between FETs of the integrated circuit; metallic-type high electrical conductivity interconnection line; and self-registering electrical connection between the gate and the interconnection line.

    18.
    发明专利
    未知

    公开(公告)号：DE69232749T2

    公开(公告)日：2003-08-07

    申请号：DE69232749

    申请日：1992-06-03

    Applicant: IBM

    Inventor： DENNARD ROBERT H ,  MEYERSON BERNARD S ,  ROSENBERG ROBERT

    IPC: H01L27/12 ,  C30B25/02 ,  C30B29/06 ,  H01L21/02 ,  H01L21/20 ,  H01L21/205 ,  H01L21/762 ,  H01L21/76 ,  H01L21/306

    Abstract: A method for fabricating silicon on insulator structures having a dislocation free silicon layer. The method utilizes low temperature UHVCVD to deposit a very heavily doped etch stop layer (12) having a very steep doping profile onto a substrate (10) and a lightly doped active layer (14) onto the etch stop layer. An insulator (16) is formed on the active layer and a carrier wafer (18) is formed on the insulator layer. The original substrate is removed in a first etch and the etch stop layer is removed in a second etch resulting in a thin, uniform active layer. In one embodiment, a small percentage of germanium is added to the etch stop layer to produce a defect free epitaxial active layer.

    FIELD EFFECT TRANSISTOR WITH SELF-ALIGNED GATE
    19.
    发明专利
    FIELD EFFECT TRANSISTOR WITH SELF-ALIGNED GATE 未知

    公开(公告)号：CA1082371A

    公开(公告)日：1980-07-22

    申请号：CA278402

    申请日：1977-05-13

    Applicant: IBM

    Inventor： DENNARD ROBERT H ,  RIDEOUT VINCENT L

    IPC: H01L27/10 ,  H01L21/28 ,  H01L21/316 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/50 ,  H01L21/44

    Abstract: FIELD EFFECT TRANSISTOR WITH SELF-ALIGNED GATE A field effect transistor (FET) with a unique gate structure is disclosed wherein the polycrystalline silicon (polysilicon) gate is self-aligned on its ends with respect to the conductive source and drain regions, and is self aligned on its sides with respect to the non-con-ductive field isolation regions. The boundaries of these conductive and nonconductive regions determine the boundaries of the channel region of the FET. This double selfalignment feature results in a polysilicon gate, the lateral dimensions and location of which correlate directly with the lateral dimensions and location of the channel region of the FET. The unique gate fabrication technique employed according to the present invention comprises delineating lithographic patterns twice in the same polysilicon layer using the same oxidation barrier masking layer; whereby the first lithographic pattern delineates the FET device regions, and the next lithographic pattern forms the gate regions wherever the two patterns cross each other (i.e., wherever they delineate a common area).

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