公开(公告)号：JPH10242478A

公开(公告)日：1998-09-11

申请号：JP1836598

申请日：1998-01-30

Applicant: IBM

Inventor： ISMAIL KHALID EZZELDIN ,  MEYERSON BERNARD S

IPC: H01L29/80 ,  H01L21/337 ,  H01L29/10 ,  H01L29/808

Abstract: PROBLEM TO BE SOLVED: To prevent strain relieving transition by providing a first type specific fourth semiconductor layer formed in the opening of a third semiconductor layer, first type specific fifth semiconductor layer formed in the opening of the fourth semiconductor layer, and a first type specific sixth semiconductor layer formed in the opening of a dielectric material layer. SOLUTION: A first type fourth semiconductor layer 30 of Si1-x Gex , where x increases with the thickness, is formed in the opening of a third semiconductor layer. A first type fifth semiconductor layer 34 of Si1-y Gey , where y is substantially constant over the entire thickness, is formed in the opening of the fourth semiconductor layer 30. A first type sixth semiconductor layer 38 of Si1-z Gez , where z decreases with the thickness, is formed in the opening of a dielectric material layer. The concentration gradient of Ge of the layers 30, 38 and selection of concentration of Ge of the layer 34 depend on mismatch of lattice of the layers 14, 16. Layers 30, 34, 38 having strain perfectly are obtained through the concentration gradient related to the thickness the layers 30, 34, 38 required for JFET 10 and strain relaxing transition is prevented.

公开(公告)号：MY120718A

公开(公告)日：2005-11-30

申请号：MYPI9800184

申请日：1998-01-16

Applicant: IBM

Inventor： ISMAIL KHALID EZZELDIN ,  MEYERSON BERNARD S

IPC: H01L29/80 ,  H01L21/20 ,  H01L21/337 ,  H01L29/10 ,  H01L29/808

Abstract: A JUNCTION FIELD EFFECT TRANSISTOR (10) AND METHOD FOR MAKING IS DESCRIBED INCORPORATING HORIZONTAL SEMICONDUCTOR LAYERS (30, 34, 38) WITHIN AN OPENING TO FORM A CHANNEL (36) AND A SEMICONDUCTOR LAYER THROUGH WHICH THE OPENING WAS MADE WHICH FORMS A GATE ELECTRODE (18, 19) SURROUNDING THE CHANNEL. THE HORIZONTAL SEMICONDUCTOR LAYERS MAY BE A SIGE ALLOY WITH GRADED COMPOSITION NEAR THE SOURCE AND DRAIN. THE INVENTION OVERCOMES THE PROBLEM OF FORMING LOW RESISTANCE JFET'S AND PROVIDES A GATE LENGTH THAT IS EASILY SCALEABLE TO SUBMICRON DIMENSIONS FOR RF, MICROWAVE, MILLIMETER AND LOGIC CIRCUITS WITHOUT SHORT CHANNEL EFFECTS.

公开(公告)号：DE69020852D1

公开(公告)日：1995-08-17

申请号：DE69020852

申请日：1990-08-17

Applicant: IBM

Inventor： PRICER WILBUR D ,  FAURE THOMAS B ,  MEYERSON BERNARD S ,  TURNBULL JOHN R ,  NESTORK WILLIAM

IPC: H01L21/302 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/334 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/00 ,  H01L27/04 ,  H01L27/06 ,  H01L27/10 ,  H01L27/108 ,  G11C11/36 ,  H01L27/102

公开(公告)号：DE68909977D1

公开(公告)日：1993-11-25

申请号：DE68909977

申请日：1989-01-27

Applicant: IBM

Inventor： BRODSKY MARC H ,  FANG FRANK F ,  MEYERSON BERNARD S

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/10 ,  H01L29/15 ,  H01L29/161 ,  H01L29/201 ,  H01L29/737 ,  H01L29/14

公开(公告)号：DE69020852T2

公开(公告)日：1996-03-14

申请号：DE69020852

申请日：1990-08-17

Applicant: IBM

Inventor： PRICER WILBUR D ,  FAURE THOMAS B ,  MEYERSON BERNARD S ,  TURNBULL JOHN R ,  NESTORK WILLIAM

IPC: H01L21/302 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/334 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/00 ,  H01L27/04 ,  H01L27/06 ,  H01L27/10 ,  H01L27/108 ,  G11C11/36 ,  H01L27/102

公开(公告)号：CA1328796C

公开(公告)日：1994-04-26

申请号：CA544049

申请日：1987-08-07

Applicant: IBM

Inventor： MEYERSON BERNARD S

IPC: C23C16/24 ,  C30B25/02 ,  C30B29/06 ,  H01L21/205

Abstract: A method and apparatus for depositing single crystal, epitaxial films of silicon on a plurality of substrates in a hot wall, isothermal deposition system is described. The deposition temperatures are less than about 800.degree.C, and the operating pressures during deposition are such that non-equilibrium growth kinetics determine the deposition of the silicon films. An isothermal bath gas of silicon is produced allowing uniform deposition of epitaxial silicon films simultaneously on multiple substrates. This is a flow system in which means are provided for establishing an ultrahigh vacuum in the range of aobut 10-9 Torr prior to epitaxial deposition. The epitaxial silicon layers can be doped in-situ to provide very abruptly defined regions of either n- or p-type conductivity.

公开(公告)号：BR9201914A

公开(公告)日：1993-01-12

申请号：BR9201914

申请日：1992-05-21

Applicant: IBM

Inventor： LEGOUES FRANCOISE K ,  MEYERSON BERNARD S

IPC: G02B6/13 ,  H01L21/20 ,  H01L29/15 ,  H01L31/028 ,  H01L31/036 ,  H01L31/18 ,  H01S5/32 ,  H01S5/327 ,  H01S3/18

Abstract: A multi-layered structure (10) and process for forming it are described, incorporating a single crystal substrate (12), a plurality of epitaxial layers (16, 18, 22, 40, 42, 44, 48) having graded composition wherein the layers have changing lattice spacings not exceeding about 2 percent per 100,0 nm of thickness whereby misfit dislocations (54 ... 59) are formed to relieve strain and then move to the edges of respective layers. The invention overcomes the problem of large numbers of misfit dislocations threading to the surface of the top layer, especially during device processing at at temperatures in a range from 700 to 900 degrees Celsius. Fully relaxed, incommensurate structures having low defect densities are obtained, where arbitrary combinations of materials can be used.

公开(公告)号：CA2062134A1

公开(公告)日：1992-12-01

申请号：CA2062134

申请日：1992-03-02

Applicant: IBM

Inventor： LEGOUES FRANCOISE K ,  MEYERSON BERNARD S

IPC: G02B6/13 ,  H01L21/20 ,  H01L29/15 ,  H01L31/028 ,  H01L31/036 ,  H01L31/18 ,  H01S5/32 ,  H01S5/327 ,  H01L29/02 ,  H01S3/025 ,  H01S3/08 ,  G02B6/12 ,  G02B5/20

Abstract: Y09-91-061 LOW DEFECT DENSITY/ARBITRARY LATTICE CONSTANT HETEROEPITAXIAL LAYERS of the Invention A multi-layered structure and process for forming it are described, incorporating a single crystal substrate, a plurality of epitaxial layers having graded composition wherein the layers have changing lattice spacings not exceeding about 2 percent per 1000.ANG. of thickness whereby misfit dislocations are formed to relieve strain and then move to the edges of respective layers. The invention overcomes the problem of large numbers of misfit dislocations threading to the surface of the top layer, especially during device processing at at temperatures in a range from 700 to 900 degrees Celsius. Fully relaxed, incommensurate structures having low defect densities are obtained, where arbitrary combinations of materials can be used.

公开(公告)号：CA2040660A1

公开(公告)日：1991-12-01

申请号：CA2040660

申请日：1991-04-17

Applicant: IBM

Inventor： MEYERSON BERNARD S

IPC: H01L21/205 ,  H01L21/22 ,  H01L21/331 ,  H01L29/73 ,  H01L29/737

Abstract: An in-situ doped n-type silicon layer is provided by a low temperature, low pressure chemical vapor deposition process employing a germanium-containing gas in combination with the n-type dopant containing gas to thereby enhance the in-situ incorporation of the n-type dopant into the silicon layer as an electronically active dopant. Also provided are a silicon layer including a P-N junction wherein the layer contains an n-type dopant and germanium, and devices such as transistors incorporating an in-situ n-doped silicon layer.

公开(公告)号：DE69232749D1

公开(公告)日：2002-10-02

申请号：DE69232749

申请日：1992-06-03

Applicant: IBM

Inventor： DENNARD ROBERT H ,  MEYERSON BERNARD S ,  ROSENBERG ROBERT

IPC: H01L27/12 ,  C30B25/02 ,  C30B29/06 ,  H01L21/02 ,  H01L21/20 ,  H01L21/205 ,  H01L21/762 ,  H01L21/76 ,  H01L21/306

Abstract: A method for fabricating silicon on insulator structures having a dislocation free silicon layer. The method utilizes low temperature UHVCVD to deposit a very heavily doped etch stop layer (12) having a very steep doping profile onto a substrate (10) and a lightly doped active layer (14) onto the etch stop layer. An insulator (16) is formed on the active layer and a carrier wafer (18) is formed on the insulator layer. The original substrate is removed in a first etch and the etch stop layer is removed in a second etch resulting in a thin, uniform active layer. In one embodiment, a small percentage of germanium is added to the etch stop layer to produce a defect free epitaxial active layer.