公开(公告)号：FR2337402A1

公开(公告)日：1977-07-29

申请号：FR7635304

申请日：1976-11-19

Applicant: IBM

Inventor： CHRISTIE KENNETH H ,  DEWITT DAVID ,  JOHNSON WILLIAM S

IPC: H01L21/8247 ,  G11C16/04 ,  H01L21/336 ,  H01L27/088 ,  H01L29/10 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34 ,  H01L21/74 ,  H01L27/04

Abstract: A metal nitride oxide semiconductor device capable of use within a memory cell, having a more heavily doped region of the same type as the substrate provided directly under the channel of the depletion mode device. Application of a positive write voltage to the gate of the device, with the substrate at 0 volts potential and the source and drain biased to a suitable positive level, results in avalanche operation of the device whereby charge is stored in a nitride oxide interface under the gate, thereby converting the device to enhancement mode operation. The charge can be removed with the source and drain biased to the 0 volt potential of the substrate and a positive erase signal applied to the gate. A four device memory cell is disclosed.

公开(公告)号：GB1270226A

公开(公告)日：1972-04-12

申请号：GB26171

申请日：1971-01-04

Applicant: IBM

Inventor： DEWITT DAVID ,  DHAKA VIR ABHIMANYU ,  OBERAI AVTAR SINGH

IPC: H01L23/522 ,  H01L21/283 ,  H01L21/329 ,  H01L21/331 ,  H01L21/768 ,  H01L23/29 ,  H01L23/485 ,  H01L29/73

Abstract: 1,270,226. Transistors. INTERNATIONAL BUSINESS MACHINES CORP. 4 Jan., 1971 [9 Jan., 1970], No. 261/71. Heading H1K. In making a transistor a layer of silicon dioxide and a superposed layer of silicon nitride are formed on the base region, an aperture opened in the layers and impurity diffused through it to form the emitter region, a further base contact aperture opened in the layers and metal deposited over the layers and in this aperture to form a base contact, a further layer of silicon dioxide deposited overall and then selectively etched to re-expose the emitter region and metal deposited on this layer and the emitter region to form an emitter contact. In the embodiment (Fig. 9) the metal layers 7, 10 are aluminium, or molybdenum on platinum, and the emitter is diffused prior to formation of the base contact apertures. Conventional processes, which are described, are used to form the oxide layers 2, 8a and nitride layer 3, and the first metal layer, 7 of aluminium, initially deposited overall, is removed from the emitter by etching in a specified phosphoric-nitric acid mix. In an alternative method the base contact and emitter diffusion apertures are formed simultaneously. Then a further layer of oxide is deposited overall, etched from the emitter aperture to allow the diffusion and subsequently from the base contact aperture.

公开(公告)号：MX5984E

公开(公告)日：1984-09-12

申请号：MX10099170

申请日：1970-11-10

Applicant: IBM

Inventor： DEWITT DAVID

IPC: H01L31/18

公开(公告)号：DE2358878A1

公开(公告)日：1974-07-04

申请号：DE2358878

申请日：1973-11-27

Applicant: IBM

Inventor： DEWITT DAVID

IPC: G09G3/12 ,  H01J29/04 ,  H01J31/12 ,  H01J29/50 ,  H04N3/12 ,  G09F9/32

Abstract: The display device has an electrically conductive phosphor-coated transparent screen, a panel element disposed in close parallel relation to the screen with the panel having an array of electron emitting regions on a semiconductor plate, each controlled by an adjacent memory cell in the plate. An enclosure which includes the screen surrounds the panel. An electric potential is established between the screen and the panel, and a vacuum produced in the enclosure. Preferably, the memory cells associated with the electron emitting regions are storage elements of a shift register which extend throughout the entire array of electron emitters. A binary signal is introduced into the shift register which is used to establish a predetermined pattern of electron emitting regions on the semiconductor panel. This produces a display on the spaced transparent screen when the emitted electrons strike the phosphor on the screen.

公开(公告)号：DE1943300A1

公开(公告)日：1970-03-12

申请号：DE1943300

申请日：1969-08-26

Applicant: IBM

Inventor： DEWITT DAVID ,  ROGENE GATES HARLAN ,  PLATT ALAN

IPC: H01L21/761 ,  H01L29/08 ,  H01L7/36

Abstract: 1,263,127. Integrated circuits. INTERNATIONAL BUSINESS MACHINES CORP. 19 Aug., 1969 [5 Sept., 1968], No. 41319/69. Heading H1K. An individual isolation wall surrounding each component in an I.C. is produced by diffusing a first region of the opposite conductivity type into a substrate, depositing a first epitaxial layer of the same conductivity type as the substrate, diffusing a frame region of the opposite conductivity type through the layer to contact the first region, depositing a second epitaxial layer, and diffusing a second frame region through this layer to contact the first frame region. An N--type Si wafer (10) is thermally oxidized and the oxide photolithographically processed to provide openings into which an impurity is diffused to form P-type isolation regions (12), Fig. 2a (not shown). The surface is reoxidized and all the oxide removed and an N--type epitaxial layer (16) is deposited by the hydrogen reduction of SiCl 4 , Fig. 2b (not shown). The surface is oxide masked and impurities are diffused-in to form an annular P-type region (18), Fig. 2c (not shown), and an N + -type subcollector region 20, Fig. 2d (not shown). A second N--type epitaxial layer 22 is then deposited and a P-type annular region 28, and N + -type collector contact region 24, a P-type base region 26 and an N + -type emitter region 32 are formed by diffusion. During subsequent epitaxial growth and diffusion steps the impurities in P-type regions 12 and 18 and in N-type region 20 diffuse into the overlying layers so that the transistor is completely surrounded by a P-type isolation region and the region 24 contacts the sub-collector region 20. The N + -type collector contact region 24 and the emitter region 32 may be doped with phosphorus. The base region 26 may be formed simultaneously with the P-type isolation region 28. A low resistance cross-over may be provided in the wafer by forming a P-type "column" simultaneously with the three isolation region diffusions, conductive tracks in one direction passing over the "column" on an insulating layer while a track extending at right angles to the first direction is broken and has its ends in contact with spaced parts of the top of the "column" which completes the circuits, Fig. 3 (not shown).