公开(公告)号：US3676231A

公开(公告)日：1972-07-11

申请号：US3676231D

申请日：1970-02-20

Applicant: IBM

Inventor： MEDVECKY BARTHOLOMEW P ,  OBERAI AVTAR S ,  PLATT ALAN

IPC: H01L29/73 ,  H01L21/00 ,  H01L21/22 ,  H01L21/225 ,  H01L21/331 ,  H01L7/44

CPC classification number: H01L21/2252 ,  H01L21/00

Abstract: A METHOD FOR PRODUCING A DIFFUSED BORON REGION IN A SILICON SEMICONDUCTOR HAVING AN IMPURITY PROFILE CHARACTERIZED AS A STEP FUNCTION AND HAVING A SURFACE IMPURITY CONCENTRATION LESS THAN THE SOLID SOLUBILITY OF BORON IN SILICON WHEREIN THE BODY IS EXPOSED TO A GASEOUS MIXTURE OF O2, AND BBR3, AND AN INERT CARRIER GAS AT AN ELEVATED TEMPERATURE WHICH FORMS A GLASSY BORON RICH LAYER, AND SUBSEQUENTLY HEATING THE RESULTANT BODY IN AN OXIDIZING ENVIROMENT, OR A COMBINATION OXIDIZING AND NONOXIDIZING ENVIROMENTS, TO INCREASE THE DEPTH OF THE DIFFUSED REGION AND SIMULTANEOUSLY REDUCE THE SURFACE CONCENTRATION PRODUCING A PROFILE HAVING A STEP FUNCTION CONFIGURATION.

公开(公告)号：US3547716A

公开(公告)日：1970-12-15

申请号：US3547716D

申请日：1968-09-05

Applicant: IBM

Inventor： DEWITT DAVID ,  GATES HARLAN R ,  PLATT ALAN

IPC: H01L21/761 ,  H01L29/08 ,  H01L7/36

CPC classification number: H01L29/0821 ,  H01L21/761 ,  Y10S148/037 ,  Y10S148/085 ,  Y10S148/151

公开(公告)号：US3650854A

公开(公告)日：1972-03-21

申请号：US3650854D

申请日：1970-08-03

Applicant: IBM

Inventor： DEMSKY HERBERT M ,  PLATT ALAN ,  RIDEOUT ARTHUR J ,  SAMSON ROBERT S

IPC: H01L21/00 ,  H01L21/22 ,  H01L29/00 ,  H01L29/73 ,  H01L7/44

CPC classification number: H01L29/00 ,  H01L21/00 ,  H01L21/22 ,  H01L29/73 ,  Y10S148/043 ,  Y10S148/106

Abstract: A process for producing in a transistor a slumped base profile wherein the base diffusion window is reoxidized, a layer of P2O5 is deposited over the oxide, an insulating layer deposited over the P2O5, an emitter window opened, and emitter diffusion made.

Abstract translation: 一种用于在晶体管中制造贱底基本轮廓的方法，其中基底扩散窗被再氧化，在氧化物上沉积P2O5层，沉积在P2O5上的绝缘层，打开的发射器窗口和发射极扩散。

公开(公告)号：US3649388A

公开(公告)日：1972-03-14

申请号：US3649388D

申请日：1968-11-04

Applicant: IBM

Inventor： JOSHI MADHUKAR L ,  PLATT ALAN ,  WAJDA EDWARD S

IPC: C23C16/44 ,  C30B31/06 ,  E04F17/02 ,  H01L21/00 ,  H01L21/22 ,  H01L21/223 ,  H01L21/306 ,  H01L7/44

CPC classification number: H01L21/223 ,  E04F17/02 ,  H01L21/00 ,  H01L21/306 ,  Y10S148/003 ,  Y10S148/04 ,  Y10S148/041 ,  Y10S148/079

Abstract: A METHOD OF CONCURRENTLY FORMING A SHALALOW, FLAT FRONT DIFFUSION LAYER AND A HIGH SURFACE IMPURITY CONCENTRATION IN A SEMICONDUCTOR WAFER, BY PREHEATING THE WAFER TO DIFFUSION TEMPERATURE IN AN ATMOSPHERE THAT WILL NOT FORM ANY FILM, SUCH AS AN OXIDE OR NITRIDE LAYER, UPON TH SURFACE OF THE SEMICONDUCTOR WAFER; CARRYING THE DIFFUSANT,

SUCH AS AS OR P, IN A CARRIER GAS SUCH AS ARGON THAT WILL NOT INTERFERE BY LAYER FORMATION WITH THE DIFFUSION; DIFFUSING THE AS OR P TO A DEPTH NOT EXCEEDING 20 MICROINCHES; AND THEN COOLING IN AN INERT ATOMSPHERE.

公开(公告)号：DE3276982D1

公开(公告)日：1987-09-17

申请号：DE3276982

申请日：1982-11-05

Applicant: IBM

Inventor： CHANCE DUDLEY AUGUSTUS ,  PLATT ALAN ,  HO CHUNG WEN ,  RAY SUDIPTA KUMAR

IPC: H01L23/52 ,  H01L23/538 ,  H05K1/00 ,  H05K3/22

Abstract: A chip carrying module includes a number of engineering change lines (ECX, ECY) buried below the surface of the module. The engineering change lines are interrupted periodically to provide a set of vias (48, 84; 49, 53; 54, 58) extending up to the upper surface of the module between each set of chips (10-15) where the vias are connected by dumbbell-shaped pads (45-47, 50-52, 55-57) including a narrow link (46, 51, 56) which permits laser deletion or the like. In addition, the dumbbell-shaped pads are located adjacent to the fan-out pads (41, 75) for the chips. Thus, the fan-out pads can be connected to the dumbbell-shaped pads (45, 70) by means of fly-wires (44, 74). In addition, individual engineering change lines can be connected together to reach every region of the module by connecting a fly-wire (59) from one dumbbell-shaped pad (55) to another (60). In addition, by deleting the links (46, 56, 83, 71) at such dumbbell-shaped pads, the engineering change connections are limited to the particular path required.

公开(公告)号：DE1943300A1

公开(公告)日：1970-03-12

申请号：DE1943300

申请日：1969-08-26

Applicant: IBM

Inventor： DEWITT DAVID ,  ROGENE GATES HARLAN ,  PLATT ALAN

IPC: H01L21/761 ,  H01L29/08 ,  H01L7/36

Abstract: 1,263,127. Integrated circuits. INTERNATIONAL BUSINESS MACHINES CORP. 19 Aug., 1969 [5 Sept., 1968], No. 41319/69. Heading H1K. An individual isolation wall surrounding each component in an I.C. is produced by diffusing a first region of the opposite conductivity type into a substrate, depositing a first epitaxial layer of the same conductivity type as the substrate, diffusing a frame region of the opposite conductivity type through the layer to contact the first region, depositing a second epitaxial layer, and diffusing a second frame region through this layer to contact the first frame region. An N--type Si wafer (10) is thermally oxidized and the oxide photolithographically processed to provide openings into which an impurity is diffused to form P-type isolation regions (12), Fig. 2a (not shown). The surface is reoxidized and all the oxide removed and an N--type epitaxial layer (16) is deposited by the hydrogen reduction of SiCl 4 , Fig. 2b (not shown). The surface is oxide masked and impurities are diffused-in to form an annular P-type region (18), Fig. 2c (not shown), and an N + -type subcollector region 20, Fig. 2d (not shown). A second N--type epitaxial layer 22 is then deposited and a P-type annular region 28, and N + -type collector contact region 24, a P-type base region 26 and an N + -type emitter region 32 are formed by diffusion. During subsequent epitaxial growth and diffusion steps the impurities in P-type regions 12 and 18 and in N-type region 20 diffuse into the overlying layers so that the transistor is completely surrounded by a P-type isolation region and the region 24 contacts the sub-collector region 20. The N + -type collector contact region 24 and the emitter region 32 may be doped with phosphorus. The base region 26 may be formed simultaneously with the P-type isolation region 28. A low resistance cross-over may be provided in the wafer by forming a P-type "column" simultaneously with the three isolation region diffusions, conductive tracks in one direction passing over the "column" on an insulating layer while a track extending at right angles to the first direction is broken and has its ends in contact with spaced parts of the top of the "column" which completes the circuits, Fig. 3 (not shown).

公开(公告)号：CA939829A

公开(公告)日：1974-01-08

申请号：CA89301

申请日：1970-07-28

Applicant: IBM

Inventor： PLATT ALAN ,  SANDHU JAGTAR J

IPC: H01L21/768 ,  H01L21/00 ,  H01L21/28 ,  H01L21/331 ,  H01L23/482 ,  H01L23/485 ,  H01L29/43 ,  H01L29/73

公开(公告)号：CA1182583A

公开(公告)日：1985-02-12

申请号：CA404031

申请日：1982-05-28

Applicant: IBM

Inventor： DOUGHERTY WILLIAM E ,  FEINBERG IRVING ,  HUMENIK JAMES N ,  PLATT ALAN

IPC: H01L27/04 ,  H01G2/06 ,  H01G4/06 ,  H01G4/10 ,  H01G4/12 ,  H01G4/228 ,  H01G4/30 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01G1/035 ,  H01G1/14

Abstract: THIN FILM DISCRETE DECOUPLING CAPACITOR A decoupling capacitor for mounting on an integrated circuit multi-layer ceramic. A bottom layer electrode, is evaporated or sputtered onto a carrier. A high dielectric layer is deposited followed by the upper metallurgy and a top isolating layer. Via holes are etched to respective electrode layers, ball limiting metalization deposited thereon followed by solder balls. The electrode is mounted onto the substrate, solder balls face down in contact with a compatible footprint.

公开(公告)号：DE2039255A1

公开(公告)日：1971-03-04

申请号：DE2039255

申请日：1970-08-07

Applicant: IBM

Inventor： PLATT ALAN ,  JINGH SANDHU JAGTAR

IPC: H01L21/768 ,  H01L21/00 ,  H01L21/28 ,  H01L21/331 ,  H01L23/482 ,  H01L23/485 ,  H01L29/43 ,  H01L29/73 ,  H01L

公开(公告)号：DE1955130A1

公开(公告)日：1970-05-27

申请号：DE1955130

申请日：1969-11-03

Applicant: IBM

Inventor： LAXMAN JOSHI MADHUKAR ,  PLATT ALAN ,  S WAJDA EDWARD

IPC: C23C16/44 ,  C30B31/06 ,  E04F17/02 ,  H01L21/00 ,  H01L21/22 ,  H01L21/223 ,  H01L21/306 ,  H01L7/44

Abstract: 1,266,380. Semi-conductor devices. INTERNATIONAL BUSINESS MACHINES CORP. 16 Oct., 1969 [4 Nov., 1968], No. 50865/69. Heading H1K. Impurity diffusion to a depth of less than 20 microinches is effected by preheating a semiconductor wafer in a gas which does not form a film on the surface or removes any pre-existing film, then introducing vapour of the impurity into the gas and flowing it over the wafer under continued heating to effect diffusion, and finally cooling the wafer to room temperature. Suitable gases are argon, helium, hydrogen, chlorine and hydrogen chloride. In a typical case pre-heating, to 800-1100‹ C. for Si or 650-900‹ C. for Ge and cooling both take 5 minutes. After preheating a mixture of phosphorus oxychloride and oxygen is added to the flow-and the temperature maintained-for 30 minutes. Arsenic is an alternative diffusant -in this process which yields uniform high surface concentration shallow impurity gradient junctions.