公开(公告)号：CA960772A

公开(公告)日：1975-01-07

申请号：CA134455

申请日：1972-02-10

Applicant: IBM

Inventor： COMMANDER ROBERT D ,  DIXON JERRY D

IPC: G05B19/23 ,  G05D3/14 ,  G11B5/55

Abstract: According to the present invention a movement control system comprises a motor for moving said body into a required position, a motor control unit for controlling the acceleration and deceleration of said motor, a position indicator unit producing positioning signals corresponding to movement of said body while accelerating toward said required position, and a calculating unit responsive to position data representing said required position and to said positioning signals to produce a control signal for said motor control unit to change from acceleration to deceleration in order to provide required speed/position characteristics for the movement of said body.

公开(公告)号：CA2018073A1

公开(公告)日：1990-12-19

申请号：CA2018073

申请日：1990-06-01

Applicant: IBM

Inventor： DIXON JERRY D ,  KEENER DON S ,  LOCKER HOWARD J ,  MARAZAS GERALD A ,  MCNEILL ANDREW B ,  NEWSOM THOMAS H ,  OSBORN NEAL A

IPC: G06F13/14 ,  G06F12/06

Abstract: Apparatus for assigning addresses to devices connected to an SCSI bus (10). A second configure bus (15) interconnects address assignable devices on the SCSI bus. The assignable devices may be used in a mixed system where some devices have fixed non-assignable addresses. The master device in the SCSI bus transmits configuration commands over the configuration bus and addresses for assignment over the SCSI bus. Acknowledgements are received back from a device which has accepted an address. Once configured with an address, the device propagates subsequent configuration commands to an adjacent device.

公开(公告)号：CA1228674A

公开(公告)日：1987-10-27

申请号：CA481990

申请日：1985-05-21

Applicant: IBM

Inventor： DIXON JERRY D ,  FARRELL ROBERT H ,  MARAZAS GERALD A ,  MCNEILL ANDREW B JR ,  MERCKEL GERALD U

IPC: G06F12/16 ,  G06F11/10 ,  G06F11/16 ,  G06F12/00 ,  G06F12/08 ,  G06F12/10

Abstract: REDUNDANT PAGE IDENTIFICATION FOR A CATALOGED MEMORY A redundant error-detecting addressing code for use in a cache memory. A directory converts logical data addresses to physical addresses in the cache where the data is stored in blocks. The blocks are expanded to include redundant addressing information such as the logical data address and the physical cache address. When a block is accessed from the cache, the redundant addressing is compared to the directory addressing information to confirm that the correct data has been accessed.

公开(公告)号：FR2413715B1

公开(公告)日：1986-02-21

申请号：FR7836052

申请日：1978-12-05

Applicant: IBM

Inventor： DIXON JERRY D

IPC: G06F9/46 ,  G06F9/40 ,  G06F9/42 ,  G06F9/18

公开(公告)号：CA1103365A

公开(公告)日：1981-06-16

申请号：CA314552

申请日：1978-10-27

Applicant: IBM

Inventor： DIXON JERRY D

IPC: G06F9/46 ,  G06F9/40 ,  G06F9/42 ,  G06F9/18

Abstract: RETURN AND LINK MECHANISM In a data processing system, a mechanism for enabling control to be transferred between programs, or portions thereof, that reside at different addresses in an instruction store. The initial linkage is established through the use of a Branch And Link instruction. Subsequent linkages are established through the use of Return And Link instructions, each of which causes the mechanism to transfer control to a previous program, or program segment, while simultaneously establishing the linkage for a subsequent return to this program or program segment.

公开(公告)号：CA1081856A

公开(公告)日：1980-07-15

申请号：CA277280

申请日：1977-04-29

Applicant: IBM

Inventor： DIXON JERRY D

IPC: G11B15/087 ,  G06F3/06 ,  G11B20/12 ,  G11B20/14 ,  G11B27/10 ,  G06F1/04 ,  G06F13/04

Abstract: MICROPROCESSOR SIGNAL DETECTOR A programmed processor is utilized for serial signal detection. Signals generated by double frequency magnetic recording are received by logic which is controlled, and sensed, by a sequence of program instructions from a microprocessor. In particular, a technique is disclosed by which a special pattern of signals is to be recognized. The special pattern of signals is known in the magnetic disc recording art as an address mark which is a unique pattern of interspersed clock signals and data signals. The pattern is made more unique from any other pattern of data by the fact that certain of the clock signals are missing. The ability to utilize a microprocessor, which is relatively slow, in a magnetic recording system in which the bit rate is relatively fast, is enhanced by a particular processor program instruction which is effective to access a next following instruction from program storage and then stop the clock of the processor. The clock is re-started, and therefore execution of the next instruction initiated, upon receipt of a timing signal from the logic receiving the signals to be detected.