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公开(公告)号：PH27346A
公开(公告)日：1993-06-08
申请号：PH36534
申请日：1988-02-19
Applicant: IBM
Inventor： DIXON JERRY D , SOTOMAYOR GUY GIL JR
Abstract: In a DASD caching system, in which pages of sectors of data are stored by reading in a desired sector and prefetching a plurality of adjacent sectors for later access, errors in disk storage media cause error signals to be generated. Such errors are handled by storing indications of which sectors have errors and which do not, and accessing such indications in response to later requests for such sectors. Such indications are stored in each page in the cache. Further, a history is maintained of which pages and sectors therein, were placed in the cache in the past.
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公开(公告)号：CA1176381A
公开(公告)日：1984-10-16
申请号：CA404524
申请日：1982-06-04
Applicant: IBM
Inventor： DIXON JERRY D , MARAZAS GERALD A , MERCKEL GERALD U
Abstract: DYNAMICALLY ASSIGNABLE I/O CONTROLLER CACHE In a data processing system of the type wherein a host processor transfers data to or from a plurality of attachment devices, a cache memory is provided for storing blocks of data which are most likely to be needed by the host processor in the near future. The host processor can then merely retrieve the necessary information from the cache memory without the necessity of accessing the attachment devices. When transferring data to cache from an attachment disk, additional unrequested information can be transferred at the same time if it is likely that this additional data will soon be requested. Further, a directory table is maintained wherein all data in cache is listed at a "home" position and, if more than one block of data in cache have the same home position, a conflict chaim is set-up so that checking the contents of the cache can be done simply and quickly.
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公开(公告)号：BR9004199A
公开(公告)日：1991-09-03
申请号：BR9004199
申请日：1990-08-24
Applicant: IBM
Inventor： BEALKOWSKI RICHARD , BLACKLEDGE JOHN W JR , CRONK DOYLE S , DAYAN RICHARD ALAN , KINNEAR SCOTT G , KOVACH GEORGE D , PALKA MATTHEW S JR , SACHSENMAIER ROBERT , SYVOLOSKI KEVIN MARSHALL , DIXON JERRY D , MCNEILL ANDREW B , WATCHTEL EDWARD I
Abstract: An apparatus and method for protecting BIOS stored on a direct access storage device (62) into a personal computer system (10). The personal computer system (JO) comprises a system processor (26), a system planar (24), a random access main memory (32), a read only memory (36), a protection means and at least one direct access storage device (62). The read only memory (36) includes a first portion of BIOS and data representing the type of system processor (26) and system planar (24) I/O configuration. The first portion of BIOS initializes the system (10) and the direct access storage device (62), and resets the protection means in order to read in a master boot record into the random access memory (32) from a protectable partition on the direct access storage device (62). The master boot record includes a data segment and an executable code segment. The data segment includes data representing system hardware and a system configuration which is supported by the master boot record. The first BIOS portion confirms the master boot record is compatible with the system hardware by verifying that the data from the data segment of the master boot record agrees with the system processor (26), system planar (24), and planar (24) I/O configuration. If the master boot record is compatible with the system hardware, the first BIOS portion vectors the system processor (26) to execute the executable code segment of the master boot record. The executable code segment confirms that the system configuration has not changed and loads in the remaining BIOS portion from the same protectable partition on the direct access storage device (62) into random access memory (32). The executable code segment then verifies the authenticity of the remaining BIOS portion and vectors the system processor (26) to begin executing the BIOS now in random access memory. BIOS, executing in random access memory (32), then activates the protection means to prevent further access to the protectable partition. BIOS boots up the operating system to begin operation of the personal computer system.
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公开(公告)号：CA1163724A
公开(公告)日：1984-03-13
申请号：CA361979
申请日：1980-10-07
Applicant: IBM
Inventor： DIXON JERRY D , FARRELL ROBERT H , KOPERDA FRANCIS R
Abstract: Serial Storage Interface Apparatus For Coupling Serial Storage Mechanism To A Data Processor Input/Output Bus Serial storage interface apparatus for coupling a serial storage mechanism, such as a charge coupled storage device or a magnetic bubble storage device, to a data processor input/output (I/O) bus. Speed control circuitry is provided for causing the serial storage mechanism to operate at a higher speed when the data processor is responding more rapidly to data transfer requests from the interface apparatus and at a lower speed when the data processor is responding less rapidly to data transfer requests from the interface apparatus. This speed adjustment feature reduces the amount of data buffering required for interfacing a serial storage mechanism to an asynchronous variable response time I/O bus system.
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Patent Agency Ranking
公开(公告)号：CA2018073C
公开(公告)日：1996-01-02
申请号：CA2018073
申请日：1990-06-01
Applicant: IBM
Inventor： DIXON JERRY D , KEENER DON S , LOCKER HOWARD J , MARAZAS GERALD A , MCNEILL ANDREW B , NEWSOM THOMAS H , OSBORN NEAL A
IPC: G06F13/14 , G06F12/06 , G06F13/362
Abstract: Apparatus for assigning addresses to devices connected to an SCSI bus. A second configure bus interconnects address assignable devices on the SCSI bus. The assignable devices may be used in a mixed system where some devices have fixed non-assignable addresses. The master device in the SCSI bus transmits configuration commands over the configuration bus and addresses for assignment over the SCSI bus. Acknowledgements are received back from a device which has accepted an address. Once configured with an address, the device propagates subsequent configuration commands to an adjacent device.
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公开(公告)号：CA1288870C
公开(公告)日：1991-09-10
申请号：CA558112
申请日：1988-02-04
Applicant: IBM
Inventor： DIXON JERRY D , SOTOMAYOR GUY G JR
IPC: G06F3/06 , G06F12/08 , G06F12/0866 , G06F12/16 , G11B20/18
Abstract: METHOD OF HANDLING DISK SECTOR ERRORS IN DASD CACHE In a DASD caching system, in which pages of sectors of data are stored by reading in a desired sector and prefetching a plurality of adjacent sectors for later access, errors in disk storage media cause error signals to be generated. Such errors are handled by storing indications of which sectors have errors and which do not, and accessing such indications in response to later requests for such sectors. Such indications are stored in each page in the cache. Further, a history is maintained of which pages and sectors therein, were placed in the cache in the past.
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公开(公告)号：BR9002877A
公开(公告)日：1991-08-20
申请号：BR9002877
申请日：1990-06-18
Applicant: IBM
Inventor： DIXON JERRY D , KEENER DON S , LOCKER HOWARD J , MARAZAS GERALD A , MCNEILL ANDREW B , NEWSOM THOMAS H , OSBORN NEAL A
Abstract: Apparatus for assigning addresses to devices connected to an SCSI bus (10). A second configure bus (15) interconnects address assignable devices on the SCSI bus. The assignable devices may be used in a mixed system where some devices have fixed non-assignable addresses. The master device in the SCSI bus transmits configuration commands over the configuration bus and addresses for assignment over the SCSI bus. Acknowledgements are received back from a device which has accepted an address. Once configured with an address, the device propagates subsequent configuration commands to an adjacent device.
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公开(公告)号：CA1118529A
公开(公告)日：1982-02-16
申请号：CA324854
申请日：1979-04-04
Applicant: IBM
Inventor： BROWN LEWIS W , CHISHOLM DOUGLAS R , DIXON JERRY D
Abstract: A data processor input/output controller which is particularly useful as a microcontroller for the transfer of data between a host processor and one or more peripheral input/output devices in a digital data processing system. This input/output (I/O) controller is a subchannel controller for offloading a goodly portion of the subchannel control function from the host processor. This I/O controller includes a microprocessor for assisting and supervising the controller internal operations. Also included in the controller is an automatic high-speed data bypass mechanism whereby data may be transferred from the host processor to the I/O device or vice versa without having to pass through the microprocessor and without requiring any intervention on the part of the microprocessor during such automatic transfer. Provision is made for enabling the microprocessor to perform other functions, such as the presentation of interrupts to the host processor and the servicing of additional I/O commands from the host processor concurrently with the transfer of data via the automatic bypass mechanism. This capability is particularly useful where two or more I/O devices are connected to the controller. The automatic bypass mechanism is constructed to communicate with the host processor in a cycle steal mode. A look-ahead mechanism is provided for more quickly issuing the cycle steal requests to the host processor when operating in the automatic bypass mode. BC9-78-004
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公开(公告)号：FR2349891A1
公开(公告)日：1977-11-25
申请号：FR7708590
申请日：1977-03-15
Applicant: IBM
Inventor： DIXON JERRY D
Abstract: Signals generated by double frequency magnetic recording are received by logic which is controlled, and sensed, by a sequence of program instructions from a microprocessor. In particular, a special pattern of signals is to be recognized. The special pattern of signals is known in the magnetic disc recording art as an address mark which is a unique pattern of interspersed clock signals and data signals. The pattern is made more unique from any other pattern of data by the fact that certain of the clock signals are missing. The ability to utilize a microprocessor, which is relatively slow, in a magnetic recording system in which the bit rate is relatively fast, is enhanced by a particular processor program instruction which is effective to access a next following instruction from program storage and then stop the clock of the processor. The clock is re-started, and therefore execution of the next instruction initiated, upon receipt of a timing signal from the logic receiving the signals to be detected.
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