公开(公告)号：CA1163724A

公开(公告)日：1984-03-13

申请号：CA361979

申请日：1980-10-07

Applicant: IBM

Inventor： DIXON JERRY D ,  FARRELL ROBERT H ,  KOPERDA FRANCIS R

IPC: G06F3/06 ,  G06F3/00 ,  G06F5/06 ,  G06F13/00 ,  G06F3/04 ,  G11C7/00

Abstract: Serial Storage Interface Apparatus For Coupling Serial Storage Mechanism To A Data Processor Input/Output Bus Serial storage interface apparatus for coupling a serial storage mechanism, such as a charge coupled storage device or a magnetic bubble storage device, to a data processor input/output (I/O) bus. Speed control circuitry is provided for causing the serial storage mechanism to operate at a higher speed when the data processor is responding more rapidly to data transfer requests from the interface apparatus and at a lower speed when the data processor is responding less rapidly to data transfer requests from the interface apparatus. This speed adjustment feature reduces the amount of data buffering required for interfacing a serial storage mechanism to an asynchronous variable response time I/O bus system.

公开(公告)号：CA1235231A

公开(公告)日：1988-04-12

申请号：CA478633

申请日：1985-04-09

Applicant: IBM

Inventor： BAKER ERNEST D ,  FARRELL ROBERT H ,  KATZ NEIL A ,  OVIES HERNANDO

IPC: G06F13/12 ,  G06F3/06 ,  G06F12/08 ,  G06F13/20

Abstract: I/O CONTROLLER FOR MULTIPLE DISPARATE SERIAL MEMORIES WITH A CACHE An I/O controller for disparate serial memories and a cache memory for the controller, comprising a device data flow section with a device bus linking a A buffer RAM through registers to the respective memories and to a buffer register and further comprising a cache bus linking the buffer register to a cache memory and through a channel register to the main processor. Data is transferred from the disks to the buffer register through the buffer RAM. The device and cache data flows can proceed independently.

公开(公告)号：CA1228674A

公开(公告)日：1987-10-27

申请号：CA481990

申请日：1985-05-21

Applicant: IBM

Inventor： DIXON JERRY D ,  FARRELL ROBERT H ,  MARAZAS GERALD A ,  MCNEILL ANDREW B JR ,  MERCKEL GERALD U

IPC: G06F12/16 ,  G06F11/10 ,  G06F11/16 ,  G06F12/00 ,  G06F12/08 ,  G06F12/10

Abstract: REDUNDANT PAGE IDENTIFICATION FOR A CATALOGED MEMORY A redundant error-detecting addressing code for use in a cache memory. A directory converts logical data addresses to physical addresses in the cache where the data is stored in blocks. The blocks are expanded to include redundant addressing information such as the logical data address and the physical cache address. When a block is accessed from the cache, the redundant addressing is compared to the directory addressing information to confirm that the correct data has been accessed.

公开(公告)号：AU4193585A

公开(公告)日：1985-12-19

申请号：AU4193585

申请日：1985-05-03

Applicant: IBM

Inventor： BAKER ERNEST D ,  FARRELL ROBERT H ,  KATZ NEIL A ,  OVIES HERNANDO

IPC: G06F13/12 ,  G06F3/06 ,  G06F12/08 ,  G06F13/38

Abstract: An I/O controller for disparate serial memories and a cache memory for the controller, comprising a device data flow section with a device bus linking a buffer RAM through registers to the respective memories and to a buffer register and further comprising a cache bus linking the buffer register to a cache memory and through a channel register to the main processor. Data is transferred from the disks to the buffer register through the buffer RAM. The device and cache data flows can proceed independently.