公开(公告)号：CA2018073C

公开(公告)日：1996-01-02

申请号：CA2018073

申请日：1990-06-01

Applicant: IBM

Inventor： DIXON JERRY D ,  KEENER DON S ,  LOCKER HOWARD J ,  MARAZAS GERALD A ,  MCNEILL ANDREW B ,  NEWSOM THOMAS H ,  OSBORN NEAL A

IPC: G06F13/14 ,  G06F12/06 ,  G06F13/362

Abstract: Apparatus for assigning addresses to devices connected to an SCSI bus. A second configure bus interconnects address assignable devices on the SCSI bus. The assignable devices may be used in a mixed system where some devices have fixed non-assignable addresses. The master device in the SCSI bus transmits configuration commands over the configuration bus and addresses for assignment over the SCSI bus. Acknowledgements are received back from a device which has accepted an address. Once configured with an address, the device propagates subsequent configuration commands to an adjacent device.

公开(公告)号：BR9002877A

公开(公告)日：1991-08-20

申请号：BR9002877

申请日：1990-06-18

Applicant: IBM

Inventor： DIXON JERRY D ,  KEENER DON S ,  LOCKER HOWARD J ,  MARAZAS GERALD A ,  MCNEILL ANDREW B ,  NEWSOM THOMAS H ,  OSBORN NEAL A

IPC: G06F13/14 ,  G06F12/06 ,  G06F12/00

Abstract: Apparatus for assigning addresses to devices connected to an SCSI bus (10). A second configure bus (15) interconnects address assignable devices on the SCSI bus. The assignable devices may be used in a mixed system where some devices have fixed non-assignable addresses. The master device in the SCSI bus transmits configuration commands over the configuration bus and addresses for assignment over the SCSI bus. Acknowledgements are received back from a device which has accepted an address. Once configured with an address, the device propagates subsequent configuration commands to an adjacent device.

公开(公告)号：DE3585496D1

公开(公告)日：1992-04-09

申请号：DE3585496

申请日：1985-10-15

Applicant: IBM

Inventor： DIXON JERRY DUANE ,  FARRELL ROBERT HENRI ,  MARAZAS GERALD A ,  MCNEILL JR ,  MERCKEL GERALD ULRICH

IPC: G06F12/16 ,  G06F11/10 ,  G06F11/16 ,  G06F12/00 ,  G06F12/08 ,  G06F12/10 ,  G06F11/08

Abstract: A redundant error-detecting addressing method and system for use in a cache memory. A directory converts togical data addresses to physical addresses in the cache where the data is stored in blocks. The blocks are expanded to include redundant addressing information such as the logical data address and the physical cache address. When a block is accessed from the cache, the redundant addressing is compared to the directory addressing information to confirm that the correct data has been accessed.

公开(公告)号：CA1176381A

公开(公告)日：1984-10-16

申请号：CA404524

申请日：1982-06-04

Applicant: IBM

Inventor： DIXON JERRY D ,  MARAZAS GERALD A ,  MERCKEL GERALD U

IPC: G06F12/08 ,  G06F13/12 ,  G06F13/06 ,  G11C9/06

Abstract: DYNAMICALLY ASSIGNABLE I/O CONTROLLER CACHE In a data processing system of the type wherein a host processor transfers data to or from a plurality of attachment devices, a cache memory is provided for storing blocks of data which are most likely to be needed by the host processor in the near future. The host processor can then merely retrieve the necessary information from the cache memory without the necessity of accessing the attachment devices. When transferring data to cache from an attachment disk, additional unrequested information can be transferred at the same time if it is likely that this additional data will soon be requested. Further, a directory table is maintained wherein all data in cache is listed at a "home" position and, if more than one block of data in cache have the same home position, a conflict chaim is set-up so that checking the contents of the cache can be done simply and quickly.

公开(公告)号：CA2018073A1

公开(公告)日：1990-12-19

申请号：CA2018073

申请日：1990-06-01

Applicant: IBM

Inventor： DIXON JERRY D ,  KEENER DON S ,  LOCKER HOWARD J ,  MARAZAS GERALD A ,  MCNEILL ANDREW B ,  NEWSOM THOMAS H ,  OSBORN NEAL A

IPC: G06F13/14 ,  G06F12/06

Abstract: Apparatus for assigning addresses to devices connected to an SCSI bus (10). A second configure bus (15) interconnects address assignable devices on the SCSI bus. The assignable devices may be used in a mixed system where some devices have fixed non-assignable addresses. The master device in the SCSI bus transmits configuration commands over the configuration bus and addresses for assignment over the SCSI bus. Acknowledgements are received back from a device which has accepted an address. Once configured with an address, the device propagates subsequent configuration commands to an adjacent device.

公开(公告)号：CA1228674A

公开(公告)日：1987-10-27

申请号：CA481990

申请日：1985-05-21

Applicant: IBM

Inventor： DIXON JERRY D ,  FARRELL ROBERT H ,  MARAZAS GERALD A ,  MCNEILL ANDREW B JR ,  MERCKEL GERALD U

IPC: G06F12/16 ,  G06F11/10 ,  G06F11/16 ,  G06F12/00 ,  G06F12/08 ,  G06F12/10

Abstract: REDUNDANT PAGE IDENTIFICATION FOR A CATALOGED MEMORY A redundant error-detecting addressing code for use in a cache memory. A directory converts logical data addresses to physical addresses in the cache where the data is stored in blocks. The blocks are expanded to include redundant addressing information such as the logical data address and the physical cache address. When a block is accessed from the cache, the redundant addressing is compared to the directory addressing information to confirm that the correct data has been accessed.