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    DOUBLE GATE TRANSISTOR AND METHOD OF MANUFACTURING THE SAME
    11.
    发明专利
    DOUBLE GATE TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：JP2003163356A

    公开(公告)日：2003-06-06

    申请号：JP2002276580

    申请日：2002-09-24

    Applicant: IBM

    Inventor： IEONG MEIKEI ,  EDWARD J NOWAKU

    IPC: H01L29/423 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L29/45 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

    Abstract: PROBLEM TO BE SOLVED: To provide a double gate transistor and a method of forming the same which facilitates the formation of different transistors having different threshold voltages. SOLUTION: Transistors having different body widths are formed. By forming double gate transistors with different body widths, double gate transistors having different threshold voltages can be formed without adding excessive process complexity. The formation of the double gate transistors having different threshold voltages is implemented using a fin-type double gated structure. In the fin-type structure, the double gates are formed on each side of the body, with the body being disposed horizontally between the gates. COPYRIGHT: (C)2003,JPO

    SOI FIELD EFFECT TRANSISTOR HAVING SELF CONNECTION BODY TIE
    12.
    发明专利
    SOI FIELD EFFECT TRANSISTOR HAVING SELF CONNECTION BODY TIE 失效

    公开(公告)号：JP2002009286A

    公开(公告)日：2002-01-11

    申请号：JP2001151973

    申请日：2001-05-22

    Applicant: IBM

    Inventor： JEFFREY W SLATE ,  ANDRES BRIANT ,  EDWARD J NOWAKU

    IPC: H01L29/786 ,  H01L21/84

    Abstract: PROBLEM TO BE SOLVED: To provide an SOI FET(field effect transistor) integrated circuit having an intentionally introduced parasitic FET between a body and the source of a main transistor. SOLUTION: This is an SOI NFET which regulates automatically high voltage operation by the introduction of a body tie activated in response to the voltage of the body. The body tie is activated by a parasitic FET having a body of a main transistor as a source, body being the lower side part of the main transistor, a drain short-circuited to the source of the main transistor, and a gate being an SOI substrate (having an embedded oxide layer as a gate oxide). Thus, the performance is not disadvantageous at low voltages, and a chip area is scarcely consumed.

    Semiconductor structure and method for forming semiconductor structure
    13.
    发明专利
    Semiconductor structure and method for forming semiconductor structure 有权
    用于形成半导体结构的半导体结构和方法

    公开(公告)号：JP2010153860A

    公开(公告)日：2010-07-08

    申请号：JP2009283193

    申请日：2009-12-14

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： EDWARD J NOWAKU ,  BRENT A ANDERSON

    IPC: H01L29/786

    CPC classification number: H01L29/7841 ,  H01L29/66795 ,  H01L29/785

    Abstract: PROBLEM TO BE SOLVED: To provide a body contact hybrid surface semiconductor-on-insulator (HSSOI) device formed on a semiconductor-on-insulator (SOI) substrate, and a manufacturing method thereof.
    SOLUTION: A portion of a top semiconductor layer of the SOI substrate is patterned into a semiconductor fin 18 having substantially vertical sidewalls. A portion of a body region of the semiconductor fin is exposed on a top surface of the semiconductor fin between two source regions 62 having a doping of a conductivity type opposite to a body region 20 of the semiconductor fin. A metal semiconductor alloy portion 82 is formed directly on the two source regions and the top surface of the exposed body region between the two source regions. The doping concentration of the exposed top portion of the body region can be increased by ion implantation to provide a low-resistance contact to the body region, or a recombination region having a high-density of crystalline defects can be formed.
    COPYRIGHT: (C)2010,JPO&INPIT

    Abstract translation: 解决的问题：提供一种形成在绝缘体上半导体（SOI）基板上的体接触混合表面绝缘体上半导体（HSSOI）器件及其制造方法。 解决方案：SOI衬底的顶部半导体层的一部分被图案化成具有基本垂直侧壁的半导体鳍片18。 半导体鳍片的主体区域的一部分在具有与半导体鳍片的体区域20相反的导电类型的掺杂的两个源极区域62之间的半导体鳍片的顶表面上露出。 直接在两个源极区域和两个源极区域之间的暴露体区域的顶表面上形成金属半导体合金部分82。 可以通过离子注入来增加身体区域的暴露顶部的掺杂浓度，以向身体区域提供低电阻接触，或者可以形成具有高密度结晶缺陷的复合区域。 版权所有（C）2010，JPO＆INPIT

    Method using three masks for forming final hard mask used to etch silicon fin of finfet
    16.
    发明专利
    Method using three masks for forming final hard mask used to etch silicon fin of finfet 有权
    使用三个掩模形成用于蚀刻FINFET的SILICON FIN的最终硬掩模的方法

    公开(公告)号：JP2007042790A

    公开(公告)日：2007-02-15

    申请号：JP2005224128

    申请日：2005-08-02

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： ANDERSON BRENT A ,  EDWARD J NOWAKU

    IPC: H01L21/336 ,  H01L29/786

    CPC classification number: H01L29/785 ,  H01L29/66795

    Abstract: PROBLEM TO BE SOLVED: To form a final hard mask used for etching a silicon fin of a FinFET.
    SOLUTION: A method using three masks is provided for forming a silicon mesa of a non FinFET device such as a register, a diode, a capacitor and a final hard mask used for etching a silicon fin and a silicon region of a source/drain of the FinFET. To be more specific, a first mask is used for generating a mandrel, a second mask is used for pattern-forming a side wall spacer of the mandrel, and a third mask is used for pattern-forming a box-like structure connected by one of the side spacers for positioning a gate conductor to the box-like structure.
    COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：形成用于蚀刻FinFET的硅片的最终硬掩模。 解决方案：提供了一种使用三个掩模的方法，用于形成诸如寄存器，二极管，电容器和用于蚀刻硅鳍片和源极的硅区域的最终硬掩模之类的非FinFET器件的硅台面 / FinFET。 更具体地说，使用第一掩模来产生心轴，第二掩模用于图案形成心轴的侧壁间隔物，并且第三掩模用于图案形成由一个连接的盒状结构 用于将门导体定位到盒状结构的侧面间隔件。 版权所有（C）2007，JPO＆INPIT

    Transistor equipped with polysilicon seed and its manufacturing method
    18.
    发明专利
    Transistor equipped with polysilicon seed and its manufacturing method 有权
    配有多晶硅晶体管及其制造方法

    公开(公告)号：JP2003017709A

    公开(公告)日：2003-01-17

    申请号：JP2002123022

    申请日：2002-04-24

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

    Inventor： ASSADERAGHI FARIBORZ ,  CHEN TZE-CHIANG ,  MULLER PAUL K ,  EDWARD J NOWAKU ,  SHAHIDI GHAVAM G

    IPC: H01L21/28 ,  H01L21/336 ,  H01L29/41 ,  H01L29/78 ,  H01L29/786

    CPC classification number: H01L29/66757 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78651 ,  H01L29/78675

    Abstract: PROBLEM TO BE SOLVED: To provide a design capable of manufacturing a field-effect transistor which is fine in size and contains a sub-lithography channel length on an SOI wafer or a chip with a high degree of integration through a well-known and fully-developed process. SOLUTION: A short channel effect can be effectively restrained by the use of the impurity concentration of a steep gradient which can be accurately improved in shape and arranged at a proper position, and on the other hand, impurities are injected into a polysilicon seed adjacent to the conduction channel of a transistor and diffused into the conduction channel from the polysilicon seed to relax the allowance of a process. The polysilicon seed enables a polysilicon source/drain contact, which has a structure capable of reducing its current density and path length to an irreducible minimum and giving other mechanical advantages, to grow epitaxially from the polysilicon seed.

    Abstract translation: 要解决的问题：提供一种能够制造尺寸精细并且在SOI晶片或具有高度集成度的芯片上的亚光刻通道长度通过公知的和完全的集成的场效应晶体管的设计 开发过程。 解决方案：通过使用可以精确改善形状并排列在适当位置的陡峭梯度的杂质浓度，可以有效地抑制短通道效应，另一方面，将杂质注入邻近的多晶硅晶种 晶体管的导电沟道，并且从多晶硅晶种扩散到导电沟道中以放宽工艺的余量。 多晶硅种子能够实现多晶硅源极/漏极接触，其具有能够将其电流密度和路径长度降低到不可约最小值并提供其它机械优点的结构，以从多晶硅种子外延生长。

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