公开(公告)号：EP1779436A4

公开(公告)日：2009-05-13

申请号：EP05790060

申请日：2005-06-20

Applicant: IBM

Inventor： DORIS BRUCE B ,  IEONG MEIKEI ,  NOWAK EDWARD J ,  YANG MIN

IPC: H01L27/01 ,  H01L21/20 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04 ,  H01L29/76

CPC classification number: H01L21/76251 ,  H01L21/76243 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/045 ,  H01L29/785

Abstract: A hybrid substrate having a high-mobility surface for use with planar and/or multiple-gate metal oxide semiconductor field effect transistors (MOSFETs) is provided. The hybrid substrate has a first surface portion that is optimal for n-type devices, and a second surface portion that is optimal for p-type devices. Due to proper surface and wafer flat orientations in each semiconductor layers of the hybrid substrate, all gates of the devices are oriented in the same direction and all channels are located on the high mobility surface. The present invention also provides for a method of fabricating the hybrid substrate as well as a method of integrating at least one planar or multiple-gate MOSFET thereon.

公开(公告)号：EP1565931A4

公开(公告)日：2006-04-19

申请号：EP02791319

申请日：2002-11-25

Applicant: IBM

Inventor： DORIS BRUCE B ,  CHIDAMBARRAO DURESETI ,  IEONG MEIKEI ,  MANDELMAN JACK A

IPC: H01L21/00 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/823807 ,  H01L21/823828 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843

Abstract: A semiconductor device structure, includes a PMOS device (200) and an NMOS device (300) disposed on a substrate (1, 2) the PMOS device including a compressive layer (6) stressing an active region of the PMOS device, the NMOS device including a tensile layer (9) stressing an active region of the NMOS device, wherein the compressive layer includes a first dielectric material, the tensile layer includes a second dielectric material, and the PMOS and NMOS devices are FinFET devices (200, 300).

公开(公告)号：WO03001604A2

公开(公告)日：2003-01-03

申请号：PCT/EP0206202

申请日：2002-06-06

Applicant: IBM ,  IBM DEUTSCHLAND

Inventor： BRYANT ANDRES ,  IEONG MEIKEI ,  MULLER K PAUL ,  NOWAK EDWARD J ,  FRIED DAVID M ,  RANKIN JED

IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L21/28

CPC classification number: H01L29/4908 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/66795 ,  H01L29/785

Abstract: Accordingly, the present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention uses provides a double gated transistor with asymmetric gate doping, where one of the double gates is doped degenerately n-type and the other degenerately p-type. By doping on of the gates n-type, and the other p-type, the threshold voltage of the resulting device is improved. In particular, by asymmetrically doping the two gates, the resulting transistor can, with adequate doping of the body, have a threshold voltage in a range that enables low-voltage CMOS operation. For example, a transistor can be created that has a threshold voltage between 0V and 0.5V for nFETs and between 0 and -0.5V for pFETs.

Abstract translation: 因此，本发明提供一种双门控晶体管及其形成方法，其导致改进的器件性能和密度。 本发明的优选实施例提供了具有不对称栅极掺杂的双门控晶体管，其中双栅极中的一个被简并掺杂为n型，另一个为简并p型。 通过掺杂栅极n型和另一种p型，所得器件的阈值电压得到改善。 特别地，通过不对称地掺杂两个栅极，所得到的晶体管可以通过适当掺杂的体，在允许低电压CMOS操作的范围内具有阈值电压。 例如，可以产生对于nFET具有在0V和0.5V之间的阈值电压并且对于pFET而言在0和-0.5V之间的晶体管。

公开(公告)号：JP2003163356A

公开(公告)日：2003-06-06

申请号：JP2002276580

申请日：2002-09-24

Applicant: IBM

Inventor： IEONG MEIKEI ,  EDWARD J NOWAKU

IPC: H01L29/423 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L29/45 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a double gate transistor and a method of forming the same which facilitates the formation of different transistors having different threshold voltages. SOLUTION: Transistors having different body widths are formed. By forming double gate transistors with different body widths, double gate transistors having different threshold voltages can be formed without adding excessive process complexity. The formation of the double gate transistors having different threshold voltages is implemented using a fin-type double gated structure. In the fin-type structure, the double gates are formed on each side of the body, with the body being disposed horizontally between the gates. COPYRIGHT: (C)2003,JPO

公开(公告)号：WO2006007068A2

公开(公告)日：2006-01-19

申请号：PCT/US2005016223

申请日：2005-05-10

Applicant: IBM ,  SHANG HUILING ,  IEONG MEIKEI ,  CHU JACK OON ,  GUARINI KATHRYN W

Inventor： SHANG HUILING ,  IEONG MEIKEI ,  CHU JACK OON ,  GUARINI KATHRYN W

IPC: H01L29/06 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/10

CPC classification number: H01L21/84 ,  H01L21/823807 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/7841

Abstract: A structure and method of fabrication for PMOS devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure Ge layer, and a SiGe top layer. Fabricated buried channel PMOS devices hosted in the compressively strained Ge layer show superior device characteristics relative to similar Si devices.

Abstract translation: 公开了一种用于压缩应变Ge层中的PMOS器件的结构和制造方法。 这种器件的制造方法与标准CMOS技术兼容，并且具有完全可扩展性。 该处理包括超过50％Ge含量缓冲层，纯Ge层和SiGe顶层的选择性外延沉积。 承载在压缩应变Ge层中的制造掩埋沟道PMOS器件相对于类似的Si器件显示出优异的器件特性。

公开(公告)号：JP2004207714A

公开(公告)日：2004-07-22

申请号：JP2003413993

申请日：2003-12-11

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KEVIN K CHAN ,  GUY M COEN ,  IEONG MEIKEI ,  ROY RONNEN A ,  SOLOMON PAUL M ,  YANG MIN

IPC: H01L29/417 ,  H01L21/02 ,  H01L21/265 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/66484 ,  H01L21/26533 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7831 ,  H01L29/7834 ,  H01L29/78648

Abstract: PROBLEM TO BE SOLVED: To provide a dual-gate field effect transistor (DGFET) structure which can noticeably reduce the parasitic capacitance under its source/drain region, and its manufacturing method.
SOLUTION: This double-gate field effect transistor (DGFET) adopts new two means for reducing the parasitic capacitance under its source/drain region. One means is as follows: a silicon region outside a gate is converted into an oxide 44, while a silicon/ledge 46 adjacent to the gate 58 is protected with a first spacer having a first width. This oxidation can be performed easily by means of implantation of self-aligned oxygen ions or other ions. The other means is to have the first spacer removed and replaced with a second spacer 48 which has a width smaller than that of the first one, and a new silicon source/drain region 60 formed under a self-aligned isolation region 56 by lateral selective full overgrowth, by using the newly exposed silicon/ledge 46 as a seed. Thus, the capacitance value of a backplane 32 can be decreased, while the control of the threshold voltage is retained.
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2001267565A

公开(公告)日：2001-09-28

申请号：JP2001017484

申请日：2001-01-25

Applicant: IBM

Inventor： BOYD DIANE CATHERINE ,  HANAFI HUSSEIN IBRAHIM ,  IEONG MEIKEI ,  NATZLE WESLEY CHARLES

IPC: H01L29/43 ,  H01L21/28 ,  H01L21/302 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L21/306

Abstract: PROBLEM TO BE SOLVED: To provide a metal oxide film semiconductor field effect type(MOSFET) device, which has a gate insulator of high permittivity (permittivity higher than 7), low overlap capacity (at most 0.35 fF/μm) and a channel length shorter than the gate length as defined by lithography. SOLUTION: This method contains a damascene treatment process and a chemical oxide removal(COR) process. In the COR process, a large tape is formed on a pad oxide layer. When the pad oxide layer is combined with the gate insulator of high permittivity, low overlap capacity, short channel length and superior device characteristic can be realized, as compared with an MOSFET device which is formed by using a normal complementary metal oxide film semiconductor(CMOS) method.

公开(公告)号：WO2005124871A2

公开(公告)日：2005-12-29

申请号：PCT/US2005021674

申请日：2005-06-20

Applicant: IBM ,  DORIS BRUCE B ,  IEONG MEIKEI ,  NOWAK EDWARD J ,  YANG MIN

Inventor： DORIS BRUCE B ,  IEONG MEIKEI ,  NOWAK EDWARD J ,  YANG MIN

IPC: H01L21/20 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/04 ,  H01L29/76

CPC classification number: H01L21/76251 ,  H01L21/76243 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/045 ,  H01L29/785

Abstract: A hybrid substrate having a high-mobility surface for use with planar and/or multiple-gate metal oxide semiconductor field effect transistors (MOSFETs) is provided. The hybrid substrate has a first surface portion that is optimal for n-type devices, and a second surface portion that is optimal for p-type devices. Due to proper surface and wafer flat orientations in each semiconductor layers of the hybrid substrate, all gates of the devices are oriented in the same direction and all channels are located on the high mobility surface. The present invention also provides for a method of fabricating the hybrid substrate as well as a method of integrating at least one planar or multiple-gate MOSFET thereon.

Abstract translation: 提供了具有用于平面和/或多栅极金属氧化物半导体场效应晶体管（MOSFET）的高迁移率表面的混合衬底。 混合基板具有对于n型器件是最佳的第一表面部分和对于p型器件是最佳的第二表面部分。 由于混合衬底的每个半导体层中的适当的表面和晶片平坦取向，器件的所有栅极被定向在相同的方向上，并且所有沟道都位于高迁移率表面上。 本发明还提供了一种制造混合衬底的方法以及在其上集成至少一个平面或多栅极MOSFET的方法。

公开(公告)号：JP2004207705A

公开(公告)日：2004-07-22

申请号：JP2003409571

申请日：2003-12-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DOKUMACI OMER H ,  DORIS BRUCE B ,  HEGDE SURYANARAYAN G ,  IEONG MEIKEI ,  JONES ERIN C

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/337 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/80

CPC classification number: H01L29/66916 ,  H01L29/42316 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/802

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a double-gate type field effect transistor (DGFET) of a self-aligning planar type with a front gate and a back gate aligned.
SOLUTION: A method of manufacturing this double-gate type field effect transistor (DGFET) comprises: a process of preparing a stacked double-gate structure provided with at least a back gate 14, a back gate dielectric provided on the back gate 14, a channel layer provided on the back gate dielectric, a front gate dielectric provided on the channel layer, and a front gate 22 provided on the front gate dielectric; a process of patterning the front gate 22 of the stacked double-gate structure; a process of forming a sidewall spacer on the exposed sidewall of the pattered front gate 22; and a process of forming a carrier depletion zone at a part of the back gate and allowing the carrier depletion zone to align the back gate to the front gate.
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2003332462A

公开(公告)日：2003-11-21

申请号：JP2003109064

申请日：2003-04-14

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： MOCUTA ANDA C ,  IEONG MEIKEI ,  AMOS RICKY S ,  DAINE C BOYD ,  MOCUTA DAN M ,  CHEN HUAJIE

IPC: H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L21/823807 ,  H01L21/823828

Abstract: PROBLEM TO BE SOLVED: To provide a high performance (surface channel) CMOS device provided with a mid gap work function metal gate.
SOLUTION: An epitaxial layer is used for adjustment/reduction of a threshold voltage V
t of PFET region and large amount of reduction in V
t (up to 500 mV) which are required by a CMOS device provided with a mid gap metal gate. In this case, the counter doping using an in-site B (boron) doped epitaxial layer or B and C (carbon) codoped epitaxial layer is provided. Here, the doping of C is important to give a surface channel CMOS device provided with the mid gap metal gate while an excellent short channel effect is maintained by holding the shallow B profile through the additional degree of freedom to relaxing the diffusion of B (even in the case of the subsequent activation heat cycle).
COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：提供一种具有中间间隙功能金属栅极的高性能（表面通道）CMOS器件。 解决方案：使用外延层来调整/降低PFET区域的阈值电压V t ，并且V T 的大量还原（高达500mV ），这是由设置有中间间隙金属栅极的CMOS器件所需要的。 在这种情况下，提供使用现场B（硼）掺杂外延层或B和C（碳）共掺杂外延层的反掺杂。 这里，C的掺杂对于提供具有中间间隙金属栅极的表面沟道CMOS器件而言是重要的，同时通过保持浅的B分布通过附加的自由度来放宽B的扩散（甚至 在随后的活化热循环的情况下）。 版权所有（C）2004，JPO