公开(公告)号：FR2404308A1

公开(公告)日：1979-04-20

申请号：FR7824961

申请日：1978-08-21

Applicant: IBM

Inventor： FANG FRANK FU ,  SHIH KWANG KUO

IPC: H01L27/15 ,  H01L33/00

Abstract: Multicolor light emitting diode arrays can be made using a binary semiconductor substrate on which is grown a graded epitaxial region of an AB1-xCx semiconductor. Diodes emitting various light colors can selectively be formed in different regions of the gradient by etching away a portion of the graded region. Arrays of colored light emitting diodes can be made by the techniques of diffusion and selective etching of the graded material.

公开(公告)号：DE2838818A1

公开(公告)日：1979-03-29

申请号：DE2838818

申请日：1978-09-06

Applicant: IBM

Inventor： FANG FRANK FU ,  SHIH KWANG KUO

IPC: H01L27/15 ,  H01L33/00

Abstract: Multicolor light emitting diode arrays can be made using a binary semiconductor substrate on which is grown a graded epitaxial region of an AB1-xCx semiconductor. Diodes emitting various light colors can selectively be formed in different regions of the gradient by etching away a portion of the graded region. Arrays of colored light emitting diodes can be made by the techniques of diffusion and selective etching of the graded material.

公开(公告)号：DE2611159A1

公开(公告)日：1977-02-03

申请号：DE2611159

申请日：1976-03-17

Applicant: IBM

Inventor： FANG FRANK FU ,  HERRELL DENNIS JAMES

IPC: H01L39/22 ,  H02M7/21 ,  H03K17/92 ,  H03K19/195 ,  G11C11/44

公开(公告)号：GB1081368A

公开(公告)日：1967-08-31

申请号：GB5160064

申请日：1964-12-18

Applicant: IBM

Inventor： FANG FRANK FU

IPC: H01L29/267 ,  H01L29/43 ,  H01L29/778

Abstract: 1,081,368. Unipolar transistors. INTERNATIONAL BUSINESS MACHINES CORPORATION. Dec. 18, 1964 [Dec. 26, 1963], No. 51600/64. Heading H1K. A unipolar transistor Fig. 1A comprises a semi-conductor body 2 of one conductive type with spaced source and drain regions 3, 4 of the opposite conductivity type on one surface and an epitaxially grown gate region 5 of a larger bandgap semi-conductor also of opposite conductivity type bridging regions 3, 4 so doped that under zero bias conditions an inversion layer constituting the conduction channel of the device is formed on the surface of body 2. Typically the body is of P-type gallium-doped germanium, the regions formed by arsenic diffusion or epitaxial deposition and the gate region formed of N-type gallium arsenide deposited epitaxially from the vapour phase. Alternatively the conductivity types of the various regions may be reversed. Boundary conditions at the various interfaces in the device are discussed in the Specification.

公开(公告)号：DE3779202D1

公开(公告)日：1992-06-25

申请号：DE3779202

申请日：1987-06-26

Applicant: IBM

Inventor： BRODSKY MARC HERBERT ,  FANG FRANK FU

IPC: H01L27/12 ,  H01L23/482 ,  H01L29/78 ,  H01L29/786

Abstract: A thin film transistor technology where a gate member (3) on a substrate surface (2) is in electric field influenceable proximity to active semiconductor devices in the direction normal to the substrate surface and the ohmic electrodes (32-35) of the active device are parallel with the substrate surface. The gate is formed on the substrate and conformal coatings of insulator (6) and semiconductor (31) are provided over it. A metal is deposited from the direction normal to the surface that is thicker in the horizontal dimension than the vertical so as to be susceptible to an erosion operation such as a dip etch which separates the metal into self-aligned contact areas (32, 33; 34, 35) on each side of a semiconductor device channel without additional masking. Self-alignment of the source, drain and gate can be achieved by insulator additions above and under the gate fabricated without additional masking.

公开(公告)号：DE3676536D1

公开(公告)日：1991-02-07

申请号：DE3676536

申请日：1986-04-11

Applicant: IBM

Inventor： FANG FRANK FU ,  GROSSMAN BERTRAND M

IPC: H01L29/78 ,  H01L21/033 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8236 ,  H01L29/41 ,  H01L29/423 ,  H01L21/00 ,  H01L29/10 ,  H01L29/60

Abstract: A semiconductor device (Field Effect Transistor) is fabricated by coating a wafer with oxygen impervious silicon nitride and thereafter oxidising an exposed surface. By vertically etching the oxide layer by means of reactive ion etching, an oxide abutment or bird-beak (24) is formed with a perpendicular wall (40) and sloping roof (42). By depositing an electrically conductive conformal layer (46) of thickness equal to a desired electrode length and then vertically etching this conductive layer, an electrode (16) of short length is left on the perpendicular wall (40) of the abutment or bird-beak (24). … Source and drain regions (12 and 14) are formed by ion implantation adjacent the abutment or bird-beak (24) joined by a charge conduction channel (50) which is partially constricted due to the doping profile produced by the varying thickness of the oxide layer to establish a predetermined resistance and protection from avalanche breakdown.

公开(公告)号：DE3672627D1

公开(公告)日：1990-08-23

申请号：DE3672627

申请日：1986-02-25

Applicant: IBM

Inventor： BRODSKY MARC HERBERT ,  FANG FRANK FU

IPC: H01L27/088 ,  H01L21/338 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/11 ,  H01L29/778 ,  H01L29/78 ,  H01L29/812 ,  H01L27/08

公开(公告)号：AU2176377A

公开(公告)日：1978-08-03

申请号：AU2176377

申请日：1977-01-28

Applicant: IBM

Inventor： HERRELL DENNIS JAMES ,  FANG FRANK FU

IPC: G11C19/32 ,  G05F3/02 ,  G11C11/44 ,  H03K17/92 ,  H03K19/00 ,  H03K19/195 ,  H01L39/22 ,  H03K23/24

Abstract: An alternating current powering arrangement for use with Josephson junction devices which have bilateral gain characteristics is disclosed. Using an alternating current input to a Josephson junction logic circuit, it is possible to carry out a desired binary logic function during one half of an alternating current cycle; reset the logic circuit; and carry out a different binary logic function during the second half of the alternating current cycle. In the instance of latching circuits, the Josephson junction logic circuits are reset by the passage of the alternating current (which is normally the gate current of the Josephson junction) through zero every half cycle. In the instance of self-resetting devices, the Josephson junctions normally reset themselves to the zero voltage state. Single phase and multiphase logic circuit powering arrangements are shown including a shift register arrangement which requires only two phases to achieve passage of information from the input to the output of the shift register. All of the arrangements shown include regulating means formed from a string of series connected Josephson junctions, the I-V characteristic of which effectively clips both positive and negative portions of the applied alternating current. Also included is a scheme for powering the logic gates with a constant voltage source and the parallel arrangement thereof which provides stable and isolated logic circuits. Under such circumstances, the maximum value of current applied to the logic circuits is carefully controlled and a plurality of logic circuits may be connected in cascade but isolated from each other across the regulator string. The logic circuits utilized are per se well known and may consist of terminated line logic circuits connected to a pair of low impedance buses via a single current defining resistance or via a pair of current defining resistances of value equal to R/2, where the value of R is large relative to the characteristic impedance of the power buses. Also shown are transformer means for applying AC current from an AC source to a logic circuit via board-to-module, module-to-chip and chip-to-logic circuit transformers.

公开(公告)号：DE2651443A1

公开(公告)日：1977-09-08

申请号：DE2651443

申请日：1976-11-11

Applicant: IBM

Inventor： HERRELL DENNIS JAMES ,  FANG FRANK FU

IPC: G11C19/32 ,  G05F3/02 ,  G11C11/44 ,  H03K17/92 ,  H03K19/00 ,  H03K19/195

Abstract: An alternating current powering arrangement for use with Josephson junction devices which have bilateral gain characteristics is disclosed. Using an alternating current input to a Josephson junction logic circuit, it is possible to carry out a desired binary logic function during one half of an alternating current cycle; reset the logic circuit; and carry out a different binary logic function during the second half of the alternating current cycle. In the instance of latching circuits, the Josephson junction logic circuits are reset by the passage of the alternating current (which is normally the gate current of the Josephson junction) through zero every half cycle. In the instance of self-resetting devices, the Josephson junctions normally reset themselves to the zero voltage state. Single phase and multiphase logic circuit powering arrangements are shown including a shift register arrangement which requires only two phases to achieve passage of information from the input to the output of the shift register. All of the arrangements shown include regulating means formed from a string of series connected Josephson junctions, the I-V characteristic of which effectively clips both positive and negative portions of the applied alternating current. Also included is a scheme for powering the logic gates with a constant voltage source and the parallel arrangement thereof which provides stable and isolated logic circuits. Under such circumstances, the maximum value of current applied to the logic circuits is carefully controlled and a plurality of logic circuits may be connected in cascade but isolated from each other across the regulator string. The logic circuits utilized are per se well known and may consist of terminated line logic circuits connected to a pair of low impedance buses via a single current defining resistance or via a pair of current defining resistances of value equal to R/2, where the value of R is large relative to the characteristic impedance of the power buses. Also shown are transformer means for applying AC current from an AC source to a logic circuit via board-to-module, module-to-chip and chip-to-logic circuit transformers.

公开(公告)号：FR2316748A1

公开(公告)日：1977-01-28

申请号：FR7605140

申请日：1976-02-17

Applicant: IBM

Inventor： FANG FRANK FU ,  HERRELL DENNIS J

IPC: H01L39/22 ,  H02M7/21 ,  H03K17/92 ,  H03K19/195 ,  H03K19/02