-
公开(公告)号：CA2366898A1
公开(公告)日：2000-09-14
申请号：CA2366898
申请日：2000-03-03
Applicant: IBM
Inventor： FERRAIOLO FRANK DAVID , DREPS DANIEL MARK , GOWER KEVIN CHARLES
Abstract: An elastic interface apparatus and method are implemented. The elastic interface includes a plurality of storage units for storing a stream of data values, wherein each storage unit sequentially stores members of respective sets of data values. Each data value is stored for a predetermined number of periods of a local clock. Selection circuitry may be coupled to the storage units to select the respective data value from the data stream for storage i n the corresponding storage unit. Data is sequentially output from each storag e unit in synchrony with the local clock on a target cycle of the local clock.
-
公开(公告)号：PL350133A1
公开(公告)日：2002-11-04
申请号：PL35013300
申请日：2000-03-03
Applicant: IBM
Inventor： DREPS DANIEL MARK , FERRAIOLO FRANK DAVID , GOWER KEVIN CHARLES
Abstract: An elastic interface apparatus and method are implemented. The elastic interface includes a plurality of storage units for storing for storing a stream of data values, wherein each storage unit sequentially stores members of respective sets of data values. Each data value is stored for a predetermined number of periods of a local clock. Selection circuitry may be coupled to the storage units to select the respective data value from the data stream for storage in the corresponding storage unit. Data is sequentially output from each storage unit in synchrony with the local clock on a target cycle of the local clock.
-
公开(公告)号：DE69522267T2
公开(公告)日：2002-06-13
申请号：DE69522267
申请日：1995-02-03
Applicant: IBM
Inventor： FERRAIOLO FRANK DAVID , CAPOWSKI ROBERT STANLEY , CASPER DANIEL FRANCIS , JORDAN RICHARD CARROLL , LAVIOLA WILLIAM CONSTANTINO
Abstract: A self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individualy phase aligned with the clock signal. The received clock signal is used to define boundary edges of a data bit cell individually for each line and the data on each line of the bus is individually phase adjusted so that, for example, a data transition position is in the center of the cell.
-
公开(公告)号：BR0009250A
公开(公告)日：2001-11-27
申请号：BR0009250
申请日：2000-03-03
Applicant: IBM
Inventor： DREPS DANIEL MAR , FERRAIOLO FRANK DAVID , GOWER KEVIN CHARLES
Abstract: An elastic interface apparatus and method are implemented. The elastic interface includes a plurality of storage units for storing for storing a stream of data values, wherein each storage unit sequentially stores members of respective sets of data values. Each data value is stored for a predetermined number of periods of a local clock. Selection circuitry may be coupled to the storage units to select the respective data value from the data stream for storage in the corresponding storage unit. Data is sequentially output from each storage unit in synchrony with the local clock on a target cycle of the local clock.
-
公开(公告)号：BR0009251A
公开(公告)日：2001-11-20
申请号：BR0009251
申请日：2000-03-03
Applicant: IBM
Inventor： DREPS DANIEL MARK , FERRAIOLO FRANK DAVID , GOWER KEVIN CHARLES
Abstract: An apparatus and method for a dynamic wave-pipelined interface are implemented. Data signals received from a sending circuit delayed via a programmable delay device corresponding to each signal before being latched into the receiving device. The programmable delay in each delay device is set according to an initialization procedure whereby each signal is deskewed to a latest arriving signal. Additionally, a phase of an input/output (I/O) clock controlling the latching of the data signals is adjusted so that a latching transition is substantially centered in a data valid window.
-
Patent Agency Ranking
公开(公告)号：DE69522267D1
公开(公告)日：2001-09-27
申请号：DE69522267
申请日：1995-02-03
Applicant: IBM
Inventor： FERRAIOLO FRANK DAVID , CAPOWSKI ROBERT STANLEY , CASPER DANIEL FRANCIS , JORDAN RICHARD CARROLL , LAVIOLA WILLIAM CONSTANTINO
Abstract: A self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individualy phase aligned with the clock signal. The received clock signal is used to define boundary edges of a data bit cell individually for each line and the data on each line of the bus is individually phase adjusted so that, for example, a data transition position is in the center of the cell.
-
公开(公告)号：CA2365288A1
公开(公告)日：2000-09-14
申请号：CA2365288
申请日：2000-03-03
Applicant: IBM
Inventor： FERRAIOLO FRANK DAVID , GOWER KEVIN CHARLES , DREPS DANIEL MARK
Abstract: An apparatus and method for a dynamic wave-pipelined interface are implemented. Data signals received from a sending circuit delayed via a programmable delay device corresponding to each signal before being latched into the receiving device. The programmable delay in each delay device is se t according to an initialisation procedure whereby each signal is deskewed to a latest arriving signal. Additionally, a phase of an input/output (I/O) clock controlling the latching of the data signals is adjusted so that a latching transition is substantially centred in a data valid window.
-
公开(公告)号：CA2150744A1
公开(公告)日：1995-12-18
申请号：CA2150744
申请日：1995-06-01
Applicant: IBM
Inventor： FERRAIOLO FRANK DAVID , CAPOWSKI ROBERT STANLEY , CASPER DANIEL FRANCIS , JORDAN RICHARD CARROLL , LAVIOLA WILLIAM CONSTANTINO
Abstract: A self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individualy phase aligned with the clock signal. The received clock signal is used to define boundary edges of a data bit cell individually for each line and the data on each line of the bus is individually phase adjusted so that, for example, a data transition position is in the center of the cell.
-
公开(公告)号：CA2366898C
公开(公告)日：2005-04-12
申请号：CA2366898
申请日：2000-03-03
Applicant: IBM
Inventor： DREPS DANIEL MARK , FERRAIOLO FRANK DAVID , GOWER KEVIN CHARLES
Abstract: An elastic interface apparatus and method are implemented. The elastic interface includes a plurality of storage units for storing a stream of data values, wherein each storage unit sequentially stores members of respective sets of data values. Each data value is stored for a predetermined number of periods of a local clock. Selection circuitry may be coupled to the storage units to select the respective data value from the data stream for storage i n the corresponding storage unit. Data is sequentially output from each storag e unit in synchrony with the local clock on a target cycle of the local clock.
-
公开(公告)号：ES2193940T3
公开(公告)日：2003-11-16
申请号：ES00907773
申请日：2000-03-03
Applicant: IBM
Inventor： DREPS DANIEL MARK , FERRAIOLO FRANK DAVID , GOWER KEVIN CHARLES
Abstract: An elastic interface apparatus and method are implemented. The elastic interface includes a plurality of storage units for storing for storing a stream of data values, wherein each storage unit sequentially stores members of respective sets of data values. Each data value is stored for a predetermined number of periods of a local clock. Selection circuitry may be coupled to the storage units to select the respective data value from the data stream for storage in the corresponding storage unit. Data is sequentially output from each storage unit in synchrony with the local clock on a target cycle of the local clock.
-
-
-
-
-
-
-
-
-
Search Results
23
records
(took 0.019 seconds)
