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公开(公告)号：NO155520B
公开(公告)日：1986-12-29
申请号：NO802130
申请日：1980-07-15
Applicant: IBM
Inventor： CLANCY DOUGLAS EUGENE , FRANKENY RICHARD FRANCIS , OLSON GEORGE PETER
Abstract: A damping control system for a three phase stepper motor. A reluctance velocity transducer is used for each of the three phases. The output of each of the transducers is proportional to the rotational velocity of the motor. Each of the transducers is rotationally phase shifted 3.75 with respect to one another and phased to the motor rotor rotationally such that the zero voltage crossings of the transducers correspond to the zero torque crossings of the motor. During damping or detenting of the motor the selected phase has current applied to it which is equal to a predetermined fixed value plus the feedback from its associated transducer. The windings on each side of the detent position have current applied to them which is proportional to the voltage from their respective feedback transducers. The voltage in each of the windings is amplified by a selected gain constant. The current in each of the windings is such that maximum torque is applied to drive the motor to the detent position with appropriate current reversals in the windings to damp out any kinetic energy in the rotor during detenting.
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公开(公告)号：IT1148876B
公开(公告)日：1986-12-03
申请号：IT2301680
申请日：1980-06-26
Applicant: IBM
Inventor： CLANCY DOUGLAS EUGENE , FRANKENY RICHARD FRANCIS , OLSON GEORGE PETER
Abstract: A damping control system for a three phase stepper motor. A reluctance velocity transducer is used for each of the three phases. The output of each of the transducers is proportional to the rotational velocity of the motor. Each of the transducers is rotationally phase shifted 3.75 with respect to one another and phased to the motor rotor rotationally such that the zero voltage crossings of the transducers correspond to the zero torque crossings of the motor. During damping or detenting of the motor the selected phase has current applied to it which is equal to a predetermined fixed value plus the feedback from its associated transducer. The windings on each side of the detent position have current applied to them which is proportional to the voltage from their respective feedback transducers. The voltage in each of the windings is amplified by a selected gain constant. The current in each of the windings is such that maximum torque is applied to drive the motor to the detent position with appropriate current reversals in the windings to damp out any kinetic energy in the rotor during detenting.
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公开(公告)号：DE2258884A1
公开(公告)日：1973-06-20
申请号：DE2258884
申请日：1972-12-01
Applicant: IBM
Inventor： FRANKENY RICHARD FRANCIS , TUTTLE JOEY KEITH
Abstract: Variable delay circuits generate output signals representing test signals having controlled timing widths. The output signals are generated by the variable delay circuits in accordance with data received from a memory under the control of a program of instructions stored in the memory. A fixed cycle clock initiates accessing of instructions one at a time. Each instruction in turn identifies control data which is supplied at times specified by a variable cycle clock. The delay circuits are assigned delay amounts and selected at times calculated to modify signals at their input desired amounts. The delay circuits are selected individually and in combination to give a wide variety of delay amounts. If desired, external input signals may be passed through the data generator with or without modification or may be stored in the memory for subsequent use in generating output signals. Signals resulting from these various operations may be freely interspersed. The output signals may be supplied directly to test a connected system or to an intermediate storage device such as magnetic tape which may subsequently be used to test the connected system.
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公开(公告)号：PL321324A1
公开(公告)日：1997-12-08
申请号：PL32132496
申请日：1996-01-19
Applicant: IBM
Inventor： BEERS GREGORY EDWARD , FRANKENY RICHARD FRANCIS , SMADI MITHKAL MOH D
Abstract: A method and apparatus are disclosed for sending and receiving logic signals. A driver is connected to a first end of a transmission line with a predetermined impedance and first and second transmission line ends for communicating the logic signals. The driver has a source for sending the logic signals, and a reference generator connected to the source for setting the magnitude of the signals sent by the source. A receiver is connected to the second transmission line end, and has a transmission line terminator for sinking the signals, and a reference generator connected to the terminator for setting a bias of the terminator to establish a certain family of terminator impedances for sinking the signals. The driver reference generator and the receiver reference generator interactively match the terminator impedance to the transmission line for the set magnitude of the signals.
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公开(公告)号：CA2216367A1
公开(公告)日：1996-11-14
申请号：CA2216367
申请日：1996-02-23
Applicant: IBM
Inventor： FRANKENY RICHARD FRANCIS , BEERS GREGORY EDWARD , SMADI MITHKAL MOH D
Abstract: A method and apparatus are disclosed for sending and receiving logic signals responsive to external digital data input and control signals. A reference circuit (10, 22) providing a first and second reference signal is common to the signal generating and receiving circuitry. The signal generating circuitry includes a signal source (12) connected to a transmission line (24) for generating a variable level digital signal, and a reference level adjusting and switching circuit ("RLA/S circuit") (10) which is responsive to the digital data input and the first reference signal. The RLA/S circuit is connected to the signal source for selecting the level of the variable level digital signal and providing a switching signal. The signal source output is thus adjusted and switched so that the signal source generates a digital signal to the transmission line which follows the digital data input at the selected output signal level. The signal receiving circuitry includes a variable input impedance circuit (14) connected to the transmission line which is responsive to the second reference signal for receiving variable level digital signals from the transmission line. It also includes a detecting (14, 16) circuit connected to receive the variable level digital signals from the variable input impedance circuit. The detecting circuit is responsive to the first reference signal and detects logic states of the variable level digital signals as determined by the first reference signal. The detecting circuit also converts the detected logic states into corresponding logic signals of predetermined output levels.
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Patent Agency Ranking
公开(公告)号：DE69024527T2
公开(公告)日：1996-07-04
申请号：DE69024527
申请日：1990-04-24
Applicant: IBM
Inventor： FRANKENY JEROME ALBERT , FRANKENY RICHARD FRANCIS , HERMANN KARL , WUSTRAU ROLF
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公开(公告)号：CA2160501A1
公开(公告)日：1996-05-22
申请号：CA2160501
申请日：1995-10-13
Applicant: IBM
Inventor： FRANKENY JEROME ALBERT , FRANKENY RICHARD FRANCIS , IMKEN RONALD LANN , VANDERLEE KEITH ALLAN
Abstract: Method and apparatus for fabricating fine pitch pattern multilayer printed circuit boards involving laminar stackable board layers providing power distribution, signal distribution and capacitive decoupling. In one respect, the invention relates to the fabrication of board layers by beginning with a metallic core, patterning the core, selectively enclosing the core in a dielectric, selectively depositing metal to form vias, plugs and signal lines, and forming dendrites with joining metallurgy on the vias and plugs to provide stackable connection from above or below the plane of the board layer. In another aspect, the invention is directed to the use of a sol-gel process to form a thin high dielectric constant crystalline film onto a metallic sheet followed with a deposition of a metallic layer onto the high dielectric constant film. The film serves as the dielectric of a capacitor layer which is thereafter in succession patterned, covered by a dielectric, and has selectively deposited a metallic layer for interconnecting the capacitor and forming vias. The ends of the vias are thereafter subject to dendritic growth and joining metallurgy to provide stackable interconnection capability. A multilayer composite laminar stackable circuit board structure is created using, as appropriate, layers having metallic cores and layers having capacitively configured cores. The multilayer laminar stackable circuit board provides direct vertical connection between surface mounted electronic components and the power, signal and capacitive decoupling layers of the composite board through the dendrites and joining metallurgy of the via and plug formations.
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公开(公告)号：DE3852291T2
公开(公告)日：1995-05-24
申请号：DE3852291
申请日：1988-12-13
Applicant: IBM
Inventor： FRANKENY RICHARD FRANCIS , RAKES JAMES MITCHELL
IPC: H01L21/60 , H01L23/495 , H01L23/64 , H01L23/498
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公开(公告)号：DE3852291D1
公开(公告)日：1995-01-12
申请号：DE3852291
申请日：1988-12-13
Applicant: IBM
Inventor： FRANKENY RICHARD FRANCIS , RAKES JAMES MITCHELL
IPC: H01L21/60 , H01L23/495 , H01L23/64 , H01L23/498
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公开(公告)号：FI72413C
公开(公告)日：1987-05-11
申请号：FI802259
申请日：1980-07-16
Applicant: IBM
Inventor： CLANCY DOUGLAS EUGENE , FRANKENY RICHARD FRANCIS , OLSON GEORGE PETER
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