公开(公告)号：AU2003304561A1

公开(公告)日：2005-06-08

申请号：AU2003304561

申请日：2003-10-22

Applicant: IBM

Inventor： FAUCHER MARC R ,  GEORGIOU CHRISTOS J ,  RINCON ANN

IPC: G06F15/16 ,  H04L29/08

Abstract: The invention provides a method, system, and program product for managing a connection. In particular, the invention manages connection information in memory based on an expected usage of the corresponding connection. Connection information can be stored in faster memory, such as cache memory, when the connection is expected to have numerous additional messages. Similarly, the connection information for a connection not expected to have many additional messages can be swapped out of the cache memory and stored in relatively slower memory. As a result, the connection information that is more frequently used is more likely to be available in a faster memory.

公开(公告)号：CA2135507A1

公开(公告)日：1995-07-06

申请号：CA2135507

申请日：1994-11-09

Applicant: IBM

Inventor： CIESLAK RANDALL A ,  GEORGIOU CHRISTOS J ,  LI CHUNG-SHENG

IPC: H04M7/00 ,  H04L12/56 ,  H04L12/64 ,  H04Q11/04

Abstract: A packet switch system having a buffer occupancy reduction mechanism for controlling data flow through switched nodes of the system to avoid congestion and reduce required buffer storage at the nodes. For an isochronous connection, buffers are initially allocated at each switching node connection to ensure listless transmission of packets. A buffer occupancy trace for the connection is recorded and the delay time of an isochronous packet at a particular switch port is returned to a preceding switch port. The preceding switch port employs the feedback message to delay subsequent packets through the connection to reduce the queuing time at the particular switch port. Once the isochronous connection has stabilized, buffer reallocation is performed wherein a scheduler at each switch node along the connection attempts to combine buffer allocations for different isochronous connections. This occurs provided the corresponding buffer occupancy traces of the isochronous connections do not overlap. Buffer occupancy reduction is therefore accomplished through the delaying of isochronous packets propagated through the connections of the packet switch system and the reallocating of buffers initially assigned to two or more isochronous connections.

公开(公告)号：DE3885407T2

公开(公告)日：1994-05-11

申请号：DE3885407

申请日：1988-08-18

Applicant: IBM

Inventor： GEORGIOU CHRISTOS J

IPC: H04B10/02 ,  H04Q3/52

Abstract: A system for automatically optically switching optic data signals between a plurality of input optical fibers (20, 24) and selective ones of a plurality of output optical fibers (22, 26) comprising: an optical detector means (36, 38) connected to each of said input fibers (20, 24) for converting said optic data signals manifested at said respective input optical fibers to an electronic data signal; an electronic detector means (40, 42) connected to each of said output fibers (22, 26) for converting provided electronic optic data signals to optical data signals; an electronic cross-point switch composed of multiple switching planes (2, 4, 6, 8) for selectively connecting said optical detector means (36, 38) and said electronic detector means (40, 42) such that said input optical fibers and said output optical fibers are selectively connected; and a control means (12, 58, 60) for controlling said electronic cross-point switch for selectively connecting said optical detector means and said electronic detector means after an adjustable delay time which is a function of the traffic requirements of the systems.

公开(公告)号：DE3885407D1

公开(公告)日：1993-12-09

申请号：DE3885407

申请日：1988-08-18

Applicant: IBM

Inventor： GEORGIOU CHRISTOS J

IPC: H04B10/02 ,  H04Q3/52

Abstract: A system for automatically optically switching optic data signals between a plurality of input optical fibers (20, 24) and selective ones of a plurality of output optical fibers (22, 26) comprising: an optical detector means (36, 38) connected to each of said input fibers (20, 24) for converting said optic data signals manifested at said respective input optical fibers to an electronic data signal; an electronic detector means (40, 42) connected to each of said output fibers (22, 26) for converting provided electronic optic data signals to optical data signals; an electronic cross-point switch composed of multiple switching planes (2, 4, 6, 8) for selectively connecting said optical detector means (36, 38) and said electronic detector means (40, 42) such that said input optical fibers and said output optical fibers are selectively connected; and a control means (12, 58, 60) for controlling said electronic cross-point switch for selectively connecting said optical detector means and said electronic detector means after an adjustable delay time which is a function of the traffic requirements of the systems.

公开(公告)号：CA1266716A

公开(公告)日：1990-03-13

申请号：CA502798

申请日：1986-02-26

Applicant: IBM

Inventor： GEORGIOU CHRISTOS J ,  LIEN YEONG-CHANG L ,  MARUYAMA KIYOSHI

IPC: H03K17/693 ,  H04Q3/52

Abstract: SWITCHING ARRAY WITH CONCURRENT MARKING CAPABILITY A cross-point switching array in which each cross-point of the array is controlled by the output of a first memory. Each first memory is associated with a second memory. The second memories can be sequentially set by a single controller while the cross-point connections are maintained according to the first memories. The contents of all second memories are concurrently loaded into the associated first memories to simultaneously reconfigure the cross-point array.

公开(公告)号：CA1227860A

公开(公告)日：1987-10-06

申请号：CA460683

申请日：1984-08-09

Applicant: IBM

Inventor： GEORGIOU CHRISTOS J

IPC: H04Q3/545 ,  H04Q3/52 ,  H04Q3/42

Abstract: CONTROLLER FOR A CROSS-POINT SWITCHING MATRIX A controller for controlling a one-sided switching matrix comprising a plurality of circuit elements under the control of logic circuitry. The controller interprets a request for connection or disconnection, determines if it is possible, selects a path through the matrix and sends control signals to the matrix. The circuit elements are arranged in a parallel/ pipeline architecture with multiple circuit elements simultaneously operating on a request. The controller can fetch a second request while executing a first request. The result of a request is to connect or disconnect interconnection paths on the switching matrix.