公开(公告)号：EP1683032A4

公开(公告)日：2010-03-03

申请号：EP03819045

申请日：2003-10-22

Applicant: IBM

Inventor： FAUCHER MARC R ,  GEORGIOU CHRISTOS J ,  RINCON ANN

IPC: G06F15/16 ,  H04L12/56 ,  H04L29/08

CPC classification number: H04L67/2819 ,  H04L43/0811 ,  H04L43/16 ,  H04L67/2842

公开(公告)号：JP2005044361A

公开(公告)日：2005-02-17

申请号：JP2004213810

申请日：2004-07-22

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： GEORGIOU CHRISTOS J ,  GREGURICK VICTOR L ,  SALAPURA VALENTINA

IPC: G06F15/80 ,  G06F15/16 ,  G06F15/78

CPC classification number: G06F15/7832 ,  H04L49/109 ,  H04L49/602

Abstract: PROBLEM TO BE SOLVED: To provide a system-on-chip (SoC) component including a single independent multiprocessor subsystem core. SOLUTION: This SoC component includes a plurality of multiprocessors, and each multiprocessor has a local memory used for forming a processor cluster and related to it, and a switch fabric means for connecting the respective processor clusters in an SoC integrated circuit (IC). The single SoC independent multiprocessor subsystem core can execute a multi-threading operation process for an SoC device when it is structured as a DSP, a hybrid ASIC or a network processing structure. In addition, the switch fabric means is used for connecting an SoC local system bus device and the SoC processor component having the independent multiprocessor subsystem core to each other. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供包括单个独立多处理器子系统内核的片上系统（SoC）组件。 解决方案：该SoC组件包括多个多处理器，并且每个多处理器具有用于形成与之相关的处理器集群的本地存储器，以及用于连接SoC集成电路（IC）中的各个处理器集群的交换结构 ）。 当SoC设备被构造为DSP，混合ASIC或网络处理结构时，单个SoC独立多处理器子系统内核可以为SoC设备执行多线程操作过程。 此外，交换结构装置用于将SoC本地系统总线设备和具有独立多处理器子系统核心的SoC处理器组件彼此连接起来。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2005108236A

公开(公告)日：2005-04-21

申请号：JP2004280986

申请日：2004-09-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BANTZ DAVID F ,  CHESS DAVID M ,  GEORGIOU CHRISTOS J ,  KEPHART JEFFREY O ,  PICKOVER CLIFFORD A

IPC: G06Q50/00 ,  G06F15/173 ,  G06Q30/00 ,  H04L12/00 ,  H04L12/56 ,  H04L29/08 ,  H04M3/00 ,  G06F17/60

CPC classification number: H04L67/1008 ,  H04L67/1002 ,  H04L67/1029

Abstract: PROBLEM TO BE SOLVED: To provide a method for providing dynamic switching in real time between a first service provider and a second service provider capable of providing a user with service on a communication network, respectively.
SOLUTION: The method includes a step for establishing a switching standard for determining when provision of the service is switched between the first service provider and the second service provider; a step for maintaining state information related to use of the user of the service provided by the first service provider; a step for switching the provision of the service between first service and second service to be provided on the communication network based on satisfaction of the switching standard; and a step for transferring the state information to be maintained to switching time to the second service. Preferably, the dynamic switching is performed for the user in a substantially transparent form.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种在第一服务提供商和能够在通信网络上为用户提供服务的第二服务提供商之间实时提供动态切换的方法。 解决方案：该方法包括建立切换标准的步骤，用于确定何时在第一服务提供商和第二服务提供商之间切换服务; 用于维护与由第一服务提供商提供的服务的用户的使用有关的状态信息的步骤; 基于所述切换标准的满足来切换要在所述通信网络上提供的第一服务和所述第二服务之间的所述服务的提供的步骤; 以及将要维护的状态信息传送到切换时间到第二服务的步骤。 优选地，以基本上透明的形式为用户执行动态切换。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2005216283A

公开(公告)日：2005-08-11

申请号：JP2004213847

申请日：2004-07-22

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： GEORGIOU CHRISTOS J ,  GREGURICK VICTOR L ,  SALAPURA VALENTINA ,  NAIR INDIRA

IPC: G06F13/10 ,  G06F13/36 ,  H04L29/06

Abstract: PROBLEM TO BE SOLVED: To provide a single chip protocol converter integrated circuit which receives packets generated according to a first protocol type, carries out protocol conversion, the packets converted into a second protocol type are generated and output. SOLUTION: The single chip protocol converter is implemented on a system on chip (SoC) as a macro core and a protocol conversion process has no requirement for a host system resource. In a packet conversion, the packet generated according to a first protocol version level is converted and processed. And then the packet converted according to the protocol version level in the same protocol family type which is in a second protocol version level is generated. Converted macro implementation includes multi-processing functions which can be organized as to modify by adapting operating functions of a chip. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：为了提供接收根据第一协议类型生成的分组的单芯片协议转换器集成电路，执行协议转换，生成并输出转换成第二协议类型的分组。 解决方案：单芯片协议转换器作为宏核实现在片上系统（SoC）上，协议转换过程不需要主机系统资源。 在分组转换中，根据第一协议版本级别生成的分组被转换和处理。 然后生成具有第二协议版本级别的相同协议族类型中根据协议版本级别转换的分组。 转换的宏实现包括多处理功能，其可以被组织以通过调整芯片的操作功能进行修改。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：CA1245305A

公开(公告)日：1988-11-22

申请号：CA476212

申请日：1985-03-11

Applicant: IBM

Inventor： GEORGIOU CHRISTOS J

IPC: H03K17/00 ,  H04Q3/52

Abstract: FULL-DUPLEX ONE-SIDED CROSS-POINT SWITCH A full-duplex one-sided switching chip comprising externally connected lines as input/output pairs and pairs of bi-directional interconnection lines. Duplex cross-points selectively connect input/ output line pairs to the interconnection line pairs. The interconnection lines can be coupled to interconnection lines on other chips for multichip switching arrays.

公开(公告)号：CA2114569A1

公开(公告)日：1994-10-24

申请号：CA2114569

申请日：1994-01-31

Applicant: IBM

Inventor： LI CHUNG-SHENG ,  GEORGIOU CHRISTOS J

IPC: H04L29/08 ,  H04L12/64 ,  H04L12/56 ,  H04L12/52

Abstract: A method and apparatus for intermixing circuit and packet data on a shared transmission medium. With this invention, the history of gaps between transmitted circuit frames is used to predict future gap sizes. If the size of a predicted gap is larger than the size of a frame of packet data to be transmitted, then the packet data is inserted in the next gap. If a circuit data frame arrives before the completion of transmission of a packet frame, the circuit data will be stored in an insertion buffer until completion of transmission of the packet frame.

公开(公告)号：CA1217872A

公开(公告)日：1987-02-10

申请号：CA475570

申请日：1985-03-01

Applicant: IBM

Inventor： GEORGIOU CHRISTOS J ,  RAVN ANDERS P

IPC: G06F15/167 ,  C23C14/04 ,  G06F9/52 ,  G06F12/00 ,  G06F13/374 ,  G06F15/16 ,  G06F15/17 ,  G06F13/36

Abstract: DISTRIBUTED ARBITRATION FOR MULTIPLE PROCESSORS A method of arbitrating for N processors requesting access to a shared resource utilizing 2 log2N shared variables, such as electrical lines. Each processor can assert a line which is asserted if any processor is asserting it. A requesting processor asserts one of two lines for each bit of a unique processor address, the choice of line depending on the value of the bit. The processor then examines the non-asserted line to determine if it is asserted by another processor. If the other line is asserted, the requesting processor either releases its own asserted line or waits depending on the value of the address bit. Thus, priority is determined by the address values. Once a processor has successfully asserted lines for every bit of its address it is granted access. Arbitration with fairness can be obtained by dividing processors into two fairness groups and assigning a turn to one of the groups. A processor is allowed into arbitration if the turn belongs to its fairness group. Upon completing access, the processor is assigned to the other fairness group. The turn is changed when no processor of that fairness group is requesting access.

公开(公告)号：CA2114569C

公开(公告)日：1999-03-02

申请号：CA2114569

申请日：1994-01-31

Applicant: IBM

Inventor： LI CHUNG-SHENG ,  GEORGIOU CHRISTOS J

IPC: H04L29/08 ,  H04L12/64 ,  H04L12/56 ,  H04L12/52

Abstract: A method and apparatus for intermixing circuit and packet data on a shared transmission medium. With this invention, the history of gaps between transmitted circuit frames is used to predict future gap sizes. If the size of a predicted gap is larger than the size of a frame of packet data to be transmitted, then the packet data is inserted in the next gap. If a circuit data frame arrives before the completion of transmission of a packet frame, the circuit data will be stored in an insertion buffer until completion of transmission of the packet frame.

公开(公告)号：CA2074849A1

公开(公告)日：1993-05-01

申请号：CA2074849

申请日：1992-07-29

Applicant: IBM

Inventor： FRANASZEK PETER A ,  GEORGIOU CHRISTOS J

IPC: H04Q3/52 ,  G06F15/173 ,  H04Q11/04

公开(公告)号：CA1225729A

公开(公告)日：1987-08-18

申请号：CA460687

申请日：1984-08-09

Applicant: IBM

Inventor： GEORGIOU CHRISTOS J

IPC: H04Q1/16 ,  H04Q3/52 ,  H04Q3/42

Abstract: FAULT-TOLERANT ARRAY OF CROSS-POINT SWITCHING MATRICES A cross-point switch comprising an array of cross-point matrices in which internal lines are connected to external lines by tri-state buffers. The external lines can connect different switching matrices. Redundant matrices may be included to provide fault tolerance. YO9-83-064