公开(公告)号：EP1683032A4

公开(公告)日：2010-03-03

申请号：EP03819045

申请日：2003-10-22

Applicant: IBM

Inventor： FAUCHER MARC R ,  GEORGIOU CHRISTOS J ,  RINCON ANN

IPC: G06F15/16 ,  H04L12/56 ,  H04L29/08

CPC classification number: H04L67/2819 ,  H04L43/0811 ,  H04L43/16 ,  H04L67/2842

公开(公告)号：JP2001312327A

公开(公告)日：2001-11-09

申请号：JP2001070355

申请日：2001-03-13

Applicant: IBM

Inventor： FAUCHER MARC R ,  SMITH JACK R

IPC: G06F13/42 ,  G06F1/04 ,  G06F1/06 ,  G06F1/08 ,  G06F1/10 ,  H03K17/00

Abstract: PROBLEM TO BE SOLVED: To provide a data processing system having a synchronizing interface, a partitioning clock and an I/O logic controller structure. SOLUTION: This system is provided with plural processing components 22 and each of processing components (22) is provided with plural I/O logic controllers (24). Further, this system is provided with plural clock supply sources (30) for supplying clock signals and plural multiplexers (36) connected to the plural clock supply sources and at least two of I/O logic controllers. Concerning the clock signals, frequencies or skews, namely, time delays are mutually different. Under the suitable control of a clock selection register connected to the plural multiplexers, one of plural clock signals from the clock supply sources can be supplied to at least two I/O logic controllers connected to the prescribed multiplexers.

公开(公告)号：AU2003304561A1

公开(公告)日：2005-06-08

申请号：AU2003304561

申请日：2003-10-22

Applicant: IBM

Inventor： FAUCHER MARC R ,  GEORGIOU CHRISTOS J ,  RINCON ANN

IPC: G06F15/16 ,  H04L29/08

Abstract: The invention provides a method, system, and program product for managing a connection. In particular, the invention manages connection information in memory based on an expected usage of the corresponding connection. Connection information can be stored in faster memory, such as cache memory, when the connection is expected to have numerous additional messages. Similarly, the connection information for a connection not expected to have many additional messages can be swapped out of the cache memory and stored in relatively slower memory. As a result, the connection information that is more frequently used is more likely to be available in a faster memory.

公开(公告)号：DE10110567B4

公开(公告)日：2004-07-15

申请号：DE10110567

申请日：2001-03-06

Applicant: IBM

Inventor： FAUCHER MARC R ,  SMITH JACK R

IPC: G06F13/42 ,  G06F1/04 ,  G06F1/06 ,  G06F1/08 ,  G06F1/10 ,  H03K17/00

Abstract: A data processing system (20) having a synchronous interface and partitioned clock and I/O logic controller structure. The system includes a plurality of processing components (22), each having a plurality of I/O logic controllers (24). In addition, the system includes a plurality of clock sources (30) for providing clock signals and a plurality of multiplexers (36) connected to said plurality of clock sources and to at least two of said I/O logic controllers. The clock signals differ from one another in frequency or in skew, i.e., time delay. By appropriate control of clock select registers connected to the plurality of multiplexers, one of the plurality of clock signals from the clock sources may be provided to the two or more I/O logic controllers connected to a given multiplexer. This permits different groups of I/O logic controllers to receive different clock signals in parallel. As a consequence, the signal interface for the system is partitioned into multiple group with each group controlled by a separate clock.

公开(公告)号：DE10110567A1

公开(公告)日：2001-09-27

申请号：DE10110567

申请日：2001-03-06

Applicant: IBM

Inventor： FAUCHER MARC R ,  SMITH JACK R

IPC: G06F13/42 ,  G06F1/04 ,  G06F1/06 ,  G06F1/08 ,  G06F1/10 ,  H03K17/00

Abstract: System has synchronous signal interface in place of 'fixed' signal interface and uses a number of multiplexers each of which is connected to a number of clock sources, to two or more of control units and to one clock selection register. Each multiplexer supplies an output signal as an answer to a clock selection signal from clock selection register. Multiplexer output goes to two or more control units of one of the clock signals.