公开(公告)号：JP2006107528A

公开(公告)日：2006-04-20

申请号：JP2005343161

申请日：2005-11-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BLUMRICH MATTHIAS A ,  CHEN DONG ,  COTEUS PAUL W ,  GARA ALAN G ,  GIAMPAPA MARK E ,  HEIDELBERGER PHILIP ,  HOENICKE DIRK ,  OHMACHT MARTIN ,  STEINMACHER-BUROW BURHARD D ,  TAKKEN TODD E ,  VRANAS PAVLOS M

IPC: G06F11/10 ,  G06F12/08 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/20 ,  G06F12/00 ,  G06F12/02 ,  G06F12/10 ,  G06F13/00 ,  G06F13/24 ,  G06F13/38 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06F17/14 ,  H04L1/00 ,  H04L7/02 ,  H04L7/033 ,  H04L12/28 ,  H04L12/56 ,  H04L25/02 ,  H05K7/20

CPC classification number: H05K7/20836 ,  F24F11/77 ,  G06F9/52 ,  G06F9/526 ,  G06F15/17381 ,  G06F17/142 ,  G09G5/008 ,  H04L7/0338 ,  Y02B30/746

Abstract: PROBLEM TO BE SOLVED: To provide a simple mechanism for previous extraction of a discontinuous data structure such as a very long data structure repeatedly accessed in the same sequence although being discontinuously stored. SOLUTION: This application provides a method for previously extracting a discontinuous data structure which includes steps of pointing discontinuous data structures to incorporate pointers indicative of the access sequence thereof in each data structure; and previously extracting a targeted data structure based on the access sequence shown by the pointers. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于先前提取不连续数据结构的简单机制，例如以不间断地存储的方式以相同顺序重复访问的非常长的数据结构。 解决方案：本申请提供了一种用于先前提取不连续数据结构的方法，其包括指示不连续数据结构以将指示其每个数据结构中的访问序列的指针合并的步骤; 并且先前基于指针所示的访问顺序提取目标数据结构。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2000221954A

公开(公告)日：2000-08-11

申请号：JP2000014331

申请日：2000-01-24

Applicant: IBM

Inventor： ABALI BULENT ,  FRANKE HUBERTUS ,  GIAMPAPA MARK E

IPC: G06F3/14 ,  G06F3/048 ,  G06F5/01 ,  G06F5/06 ,  G09G5/00 ,  G09G5/34 ,  H04N5/228

Abstract: PROBLEM TO BE SOLVED: To provide a method for compensating the vibration and jitter of image while making a user observable the image on a display screen by compensating the movement of a display device so that the image on a display screen of the display device is practically stopped in relation to the close observation by an observer. SOLUTION: A system for stabilizing image and for correcting jitter/vibration of image includes a movement sensing circuit 42, a horizontal signal circuit 50H and a vertical signal circuit 50V for respectively receiving the output from the movement sensing circuit 42. The output from the movement sensing circuit 42 expressing the horizontal offset and the vertical offset is applied to the horizontal signal circuit 50H and the vertical signal circuit 50V in order to move an image to be displayed in the vertical direction and the horizontal direction. Furthermore, the horizontal signal circuit 50H and the vertical signal circuit 50V receive the input for expressing the processed video image signal at the main input terminal.

公开(公告)号：CA2436413C

公开(公告)日：2011-09-27

申请号：CA2436413

申请日：2002-02-25

Applicant: IBM

Inventor： BHANOT GYAN V ,  BLUMRICH MATTHIAS A ,  CHEN DONG ,  COTEUS PAUL W ,  GARA ALAN G ,  GIAMPAPA MARK E ,  HEIDELBERGER PHILIP ,  STEINMACHER-BUROW BURKHARD D ,  TAKKEN TODD E ,  VRANAS PAVLOS M

IPC: G06F11/10 ,  H04L1/18 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/20 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F13/00 ,  G06F13/24 ,  G06F13/38 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06F17/14 ,  H04J3/02 ,  H04L1/00 ,  H04L7/02 ,  H04L7/033 ,  H04L12/28 ,  H04L12/56 ,  H04L25/02 ,  H05K7/20

Abstract: Class network routing is implemented in a network such as a computer network comprising a plurality of parallel compute processors at nodes thereof. Class network routing allows a compute processor to broadcast a message to a range (one or more) of other compute processors in the computer network, such as processors in a column or a row. Normally this type of operation requires a separate message to be sent to each processor. With class network routing pursuant to the invention, a single message is sufficient, which generally reduces the total number of messages in the network as well as the latency to do a broadcast, Class network routing is also applied to dense matrix inversion algorithms on distributed memory parallel supercomputers with hardware class function (multicast) capability. This is achieved by exploiting the fact that the communication patterns of dense matrix inversion can be served by hardware class functions, which results in faster execution times.

公开(公告)号：CA2437629A1

公开(公告)日：2002-09-06

申请号：CA2437629

申请日：2002-02-25

Applicant: IBM

Inventor： VRANAS PAVLOS M ,  CHEN DONG ,  BLUMRICH MATTHIAS A ,  BHANOT GYAN V ,  STEINMACHER-BUROW BURKHARD D ,  HEIDELBERGER PHILIP ,  GIAMPAPA MARK E ,  GARA ALAN G

IPC: G06F11/10 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/20 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F13/00 ,  G06F13/24 ,  G06F13/38 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06F17/14 ,  H04L1/00 ,  H04L7/02 ,  H04L7/033 ,  H04L12/28 ,  H04L12/56 ,  H04L25/02 ,  H05K7/20

Abstract: Methods and systems for performing arithmetic functions. In accordance with a first aspect of the invention, methods and apparatus are provided, working i n conjunction of software algorithms and hardware implementation of class network routing, to achieve a very significant reduction in the time require d for global arithmetic operation on the torus. Therefore, it leads to greater scalability of applications running on large parallel machines. The inventio n involves three steps in improving the efficiency and accuracy of global operations: (1) Ensuring, when necessary, that all the nodes do the global operation on the data in the same order and so obtain a unique answer, independent of roundoff error; (2) Using the topology of the torus to minimi ze the number of hops and the bidirectional capabilities of the network to redu ce the number of time steps in the data transfer operation to an absolute minimum; and (3) Using class function routing to reduce latency in the data transfer. With the method of this invention, every single element is injecte d into the network only once and it will be stored and forwarded without any further software overhead. In accordance with a second aspect of the invention, methods and systems are provided to efficiently implement global arithmetic operations on a network that supports the global combining operations. The latency of doing such global operations are greatly reduced by using these methods (Figure 4, node0, node1, node2, node3).

公开(公告)号：AT469501T

公开(公告)日：2010-06-15

申请号：AT02721138

申请日：2002-02-25

Applicant: IBM

Inventor： CHEN DONG ,  COTEUS PAUL W ,  GARA ALAN G ,  GIAMPAPA MARK E ,  TAKKEN TODD E

IPC: G06F11/10 ,  H04L29/12 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/20 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F13/00 ,  G06F13/24 ,  G06F13/38 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06F17/14 ,  H04L1/00 ,  H04L7/02 ,  H04L7/033 ,  H04L12/28 ,  H04L12/56 ,  H04L25/02 ,  H05K7/20

Abstract: In a massively parallel system, a method and apparatus for uniquely assigning a MAC address(400) to a device encodes the MAC address with a physical location of the device(410). The method and apparatus include configuring device interconnections of the parallel system with physical topological information such as a rack number, a midplane number, a card number, and a chip number. A device or node with a physical location encoded MAC address may then be interrogated by location for test, diagnostic, and program loading purposes.

公开(公告)号：CA2437035C

公开(公告)日：2009-01-06

申请号：CA2437035

申请日：2002-02-25

Applicant: IBM

Inventor： COTEUS PAUL W ,  CHEN DONG ,  BLUMRICH MATTHIAS A ,  GARA ALAN G ,  HEIDELBERGER PHILIP ,  TAKKEN TODD E ,  GIAMPAPA MARK E ,  STEINMACHER-BUROW BURKHARD D ,  KOPSCAY GERARD V

IPC: G06F11/10 ,  G06F15/173 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/20 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F13/00 ,  G06F13/24 ,  G06F13/38 ,  G06F15/177 ,  G06F15/76 ,  G06F15/80 ,  G06F17/14 ,  H04L1/00 ,  H04L7/02 ,  H04L7/033 ,  H04L12/28 ,  H04L12/56 ,  H04L25/02 ,  H05K7/20

Abstract: A system and method for generating global asynchronous signals in a computin g structure. Particularly, a global interrupt and barrier network is implement ed that implements logic for generating global interrupt and barrier signals fo r controlling global asynchronous operations perfomed by processing elements a t selected processing nodes (12) of computing structure in accordance with a processing algorithm; and includes the physical interconnecting of the processing nodes (12) for communicating the global interrupt and barrier signals to the elements via low latency paths. The global asynchronous signa ls respectively initiate interrupt and barrier operations at the processing nod es (12) at times selected for otpimizing performance of the processing algorithms. In one embodiment, the global interrupt and barrier network is implemented in a scalable, massively parallel supercomputing device structur e comprising a plurality of processing nodes interconnected by multiple independent networks.

公开(公告)号：DE10003376B4

公开(公告)日：2004-08-05

申请号：DE10003376

申请日：2000-01-26

Applicant: IBM

Inventor： ABALI BULENT ,  FRANKE HUBERTUS ,  GIAMPAPA MARK E

IPC: G06F3/14 ,  G06F3/048 ,  G06F5/01 ,  G06F5/06 ,  G09G5/00 ,  G09G5/34 ,  H04N5/228

Abstract: An image stabilizing apparatus and method for a display device having a display screen, include a sensor for sensing a movement of the display device, and a movement compensation circuit, operatively coupled to the sensor, for compensating for the movement of the display device such that an image on the display screen of the display device remains substantially stationary in relation to an observer's gaze.

公开(公告)号：CA2437663A1

公开(公告)日：2002-09-06

申请号：CA2437663

申请日：2002-02-25

Applicant: IBM

Inventor： CHEN DONG ,  GIAMPAPA MARK E ,  HEIDELBERGER PHILIP ,  OHMACHT MARTIN ,  HOENICKE DIRK ,  BLUMRICH MATTHIAS A ,  COTEUS PAUL W ,  GARA ALAN G

IPC: G06F11/10 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/20 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F13/00 ,  G06F13/24 ,  G06F13/38 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06F17/14 ,  H04L1/00 ,  H04L7/02 ,  H04L7/033 ,  H04L12/28 ,  H04L12/56 ,  H04L25/02 ,  H05K7/20 ,  G06F15/16

Abstract: A method and apparatus for managing coherence between two processors of a tw o processor node of a multi-processor computer system. Generally the present invention relates to a software algorithm that simplifies and significantly speeds the management of cache coherence in a message passing parallel computer, and to hardware apparatus that assists this cache coherence algorithm. The software algorithm uses the opening and closing of put/get windows to coordinate the activated required to achieve cache coherence. The hardware apparatus may be an extension to the hardware address decode, that creates, in the physical memory address space of the node, an area of virtua l memory that (a) does not actually exist, and (b) is therefore able to respon d instantly to read and write requests from the processing elements.

公开(公告)号：CA2436474A1

公开(公告)日：2002-09-06

申请号：CA2436474

申请日：2002-02-25

Applicant: IBM

Inventor： COTEUS PAUL W ,  BLUMRICH MATTHIAS A ,  CHEN DONG ,  GARA ALAN G ,  HOENICKE DIRK ,  OHMACHT MARTIN ,  VRANAS PAVLOS M ,  TAKKEN TODD E ,  STEINMARCHER-BUROW BURKHARD D ,  GIAMPAPA MARK E ,  HEIDELBERGER PHILIP

IPC: G06F11/10 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/20 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F12/14 ,  G06F13/00 ,  G06F13/24 ,  G06F13/38 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06F17/14 ,  H04L1/00 ,  H04L7/02 ,  H04L7/033 ,  H04L12/28 ,  H04L12/56 ,  H04L25/02 ,  H05K7/20

Abstract: A low latency memory system access is provided in association with a weakly- ordered multiprocessor system(Fig.1). Each processor(12-1, 12-2) in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device(10) that provides support for synchronization between the multiple processors(12-1, 12-2) in the multiprocessor and the orderly sharing of the resources. A processor(12-1, 12-2) only has permissio n to access a resource when it owns the lock associated with that resource, an d an attempt by a processor(12-1, 12-2) to own a l ock requires only a single load operation, rather than a traditional atomic load followed by store, suc h that the processor(12-1, 12-2) only performs a read operation and the hardwa re locking device(10) performs a subsequent write operation rather than the processor(12-1, 12-2).

公开(公告)号：DE60236510D1

公开(公告)日：2010-07-08

申请号：DE60236510

申请日：2002-02-25

Applicant: IBM

Inventor： CHEN DONG ,  COTEUS PAUL W ,  GARA ALAN G ,  GIAMPAPA MARK E ,  TAKKEN TODD E

IPC: G06F11/10 ,  G06F15/16 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/20 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F13/00 ,  G06F13/24 ,  G06F13/38 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06F17/14 ,  H04L1/00 ,  H04L7/02 ,  H04L7/033 ,  H04L12/28 ,  H04L12/56 ,  H04L25/02 ,  H05K7/20