公开(公告)号：EP1379933A4

公开(公告)日：2007-10-17

申请号：EP02714980

申请日：2002-02-25

Applicant: IBM

Inventor： BLUMRICH MATTHIAS A ,  CHEN DONG ,  COTEUS PAUL W ,  GARA ALAN G ,  GIAMPAPA MARK E ,  HEIDELBERGER PHILIP ,  HOENICKE DIRK ,  OHMACHT MARTIN ,  STEINMARCHER-BUROW BURKHARD D ,  TAKKEN TODD E ,  VRANAS PAVLOS M

IPC: G06F11/10 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/20 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F13/00 ,  G06F13/24 ,  G06F13/38 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06F17/14 ,  H04L1/00 ,  H04L7/02 ,  H04L7/033 ,  H04L12/28 ,  H04L12/56 ,  H04L25/02 ,  H05K7/20 ,  G06F1/00

CPC classification number: H05K7/20836 ,  F24F11/77 ,  G06F9/52 ,  G06F9/526 ,  G06F15/17381 ,  G06F17/142 ,  G09G5/008 ,  H04L7/0338 ,  Y02B30/746

Abstract: A fan module including: two or more individual fans, each fan having an air movement means and a motor engaged with the air movement means for accelerating air entering each of the two or more individual fans; a temperature sensor for sensing a temperature associated with the two or more fans and for outputting a first signal corresponding to the temperature; rotational speed sensor for outputting a second signal corresponding to a rotational speed of each of the two or more fans; and a processor for receiving the first and second signals and controlling the two or more individual fans based on the first and second signals.

公开(公告)号：JP2006107528A

公开(公告)日：2006-04-20

申请号：JP2005343161

申请日：2005-11-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BLUMRICH MATTHIAS A ,  CHEN DONG ,  COTEUS PAUL W ,  GARA ALAN G ,  GIAMPAPA MARK E ,  HEIDELBERGER PHILIP ,  HOENICKE DIRK ,  OHMACHT MARTIN ,  STEINMACHER-BUROW BURHARD D ,  TAKKEN TODD E ,  VRANAS PAVLOS M

IPC: G06F11/10 ,  G06F12/08 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/20 ,  G06F12/00 ,  G06F12/02 ,  G06F12/10 ,  G06F13/00 ,  G06F13/24 ,  G06F13/38 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06F17/14 ,  H04L1/00 ,  H04L7/02 ,  H04L7/033 ,  H04L12/28 ,  H04L12/56 ,  H04L25/02 ,  H05K7/20

CPC classification number: H05K7/20836 ,  F24F11/77 ,  G06F9/52 ,  G06F9/526 ,  G06F15/17381 ,  G06F17/142 ,  G09G5/008 ,  H04L7/0338 ,  Y02B30/746

Abstract: PROBLEM TO BE SOLVED: To provide a simple mechanism for previous extraction of a discontinuous data structure such as a very long data structure repeatedly accessed in the same sequence although being discontinuously stored. SOLUTION: This application provides a method for previously extracting a discontinuous data structure which includes steps of pointing discontinuous data structures to incorporate pointers indicative of the access sequence thereof in each data structure; and previously extracting a targeted data structure based on the access sequence shown by the pointers. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于先前提取不连续数据结构的简单机制，例如以不间断地存储的方式以相同顺序重复访问的非常长的数据结构。 解决方案：本申请提供了一种用于先前提取不连续数据结构的方法，其包括指示不连续数据结构以将指示其每个数据结构中的访问序列的指针合并的步骤; 并且先前基于指针所示的访问顺序提取目标数据结构。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：DE112010003330T5

公开(公告)日：2012-06-21

申请号：DE112010003330

申请日：2010-07-19

Applicant: IBM

Inventor： EICHENBERGER ALEXANDRE ,  GARA ALAN ,  GSCHWIND MICHAEL ,  OHMACHT MARTIN

IPC: G06F12/08 ,  G06F9/00 ,  G06F15/00

Abstract: Es werden Mechanismen zur Erstellung von Prüfpunkten (1030) in einem Cachespeicher für die spekulative Versionierung (310, 1210) eines Datenverarbeitungssystems (100) bereitgestellt. Die Mechanismen führen Code innerhalb des Datenverarbeitungssystems (100) aus, wobei der Code auf Cachespeicherzeilen im Cachespeicher für die spekulative Versionierung (310, 1210) zugreift. Durch die Mechanismen wird weiterhin festgestellt (1350), ob eine erste Bedingung eintritt, die auf die Notwendigkeit des Einrichtens eines Prüfpunkts (1030) im Cachespeicher für die spekulative Versionierung (310, 1210) hinweist. Bei dem Prüfpunkt (1030) handelt es sich um eine spekulative Cachespeicherzeile, die bei Eintreten einer zweiten Bedingung, welche ein Zurückrollen der Änderungen an einer der spekulativen Cachespeicherzeile entsprechenden Cachespeicherzeile erfordert, nichtspekulativ gemacht wird. Durch die Mechanismen wird außerdem ein Prüfpunkt (1310) im Cachespeicher für die spekulative Versionierung (310, 1210) erstellt, wenn festgestellt wird, dass die erste Bedingung eingetreten ist.

公开(公告)号：CA2437663A1

公开(公告)日：2002-09-06

申请号：CA2437663

申请日：2002-02-25

Applicant: IBM

Inventor： CHEN DONG ,  GIAMPAPA MARK E ,  HEIDELBERGER PHILIP ,  OHMACHT MARTIN ,  HOENICKE DIRK ,  BLUMRICH MATTHIAS A ,  COTEUS PAUL W ,  GARA ALAN G

IPC: G06F11/10 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/20 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F13/00 ,  G06F13/24 ,  G06F13/38 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06F17/14 ,  H04L1/00 ,  H04L7/02 ,  H04L7/033 ,  H04L12/28 ,  H04L12/56 ,  H04L25/02 ,  H05K7/20 ,  G06F15/16

Abstract: A method and apparatus for managing coherence between two processors of a tw o processor node of a multi-processor computer system. Generally the present invention relates to a software algorithm that simplifies and significantly speeds the management of cache coherence in a message passing parallel computer, and to hardware apparatus that assists this cache coherence algorithm. The software algorithm uses the opening and closing of put/get windows to coordinate the activated required to achieve cache coherence. The hardware apparatus may be an extension to the hardware address decode, that creates, in the physical memory address space of the node, an area of virtua l memory that (a) does not actually exist, and (b) is therefore able to respon d instantly to read and write requests from the processing elements.

公开(公告)号：CA2436474A1

公开(公告)日：2002-09-06

申请号：CA2436474

申请日：2002-02-25

Applicant: IBM

Inventor： COTEUS PAUL W ,  BLUMRICH MATTHIAS A ,  CHEN DONG ,  GARA ALAN G ,  HOENICKE DIRK ,  OHMACHT MARTIN ,  VRANAS PAVLOS M ,  TAKKEN TODD E ,  STEINMARCHER-BUROW BURKHARD D ,  GIAMPAPA MARK E ,  HEIDELBERGER PHILIP

IPC: G06F11/10 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/20 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F12/14 ,  G06F13/00 ,  G06F13/24 ,  G06F13/38 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06F17/14 ,  H04L1/00 ,  H04L7/02 ,  H04L7/033 ,  H04L12/28 ,  H04L12/56 ,  H04L25/02 ,  H05K7/20

Abstract: A low latency memory system access is provided in association with a weakly- ordered multiprocessor system(Fig.1). Each processor(12-1, 12-2) in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device(10) that provides support for synchronization between the multiple processors(12-1, 12-2) in the multiprocessor and the orderly sharing of the resources. A processor(12-1, 12-2) only has permissio n to access a resource when it owns the lock associated with that resource, an d an attempt by a processor(12-1, 12-2) to own a l ock requires only a single load operation, rather than a traditional atomic load followed by store, suc h that the processor(12-1, 12-2) only performs a read operation and the hardwa re locking device(10) performs a subsequent write operation rather than the processor(12-1, 12-2).

公开(公告)号：CA2830605A1

公开(公告)日：2015-04-22

申请号：CA2830605

申请日：2013-10-22

Applicant: IBM CANADA

Inventor： WANG KAI-TING AMY ,  GAO YAOQING ,  BOETTIGER HANS ,  OHMACHT MARTIN

IPC: G06F9/44

Abstract: An illustrative embodiment of a computer-implemented process for a computer-implemented process for code versioning for enabling transactional memory region promotion receives a portion of candidate source code and outlines the portion of candidate source code received for parallel execution. The computer-implemented process further wraps a critical region with entry and exit routines to enter into a speculation sub-process, wherein the entry and exit routines also gather conflict statistics at runtime. The outlined code portion is executed to determine to use a particular one of multiple loop versions according to the conflict statistics gathered at run time.

公开(公告)号：GB2485083A

公开(公告)日：2012-05-02

申请号：GB201200165

申请日：2010-07-19

Applicant: IBM

Inventor： EICHENBERGER ALEXANDRE ,  GARA ALAN ,  GSCHWIND MICHAEL ,  OHMACHT MARTIN

IPC: G06F9/38 ,  G06F11/14 ,  G06F12/08

Abstract: Mechanisms for generating checkpoints (1030) in a speculative versioning cache (310, 1210) of a data processing system (100) are provided. The mechanisms execute code within the data processing system (100), wherein the code accesses cache lines in the speculative versioning cache (310, 1210). The mechanisms further determine (1350) whether a first condition occurs indicating a need to generate a checkpoint (1030) in the speculative versioning cache (310, 1210). The checkpoint (1310) is a speculative cache line which is made non-speculative in response to a second condition occurring that requires a roll-back of changes to a cache line corresponding to the speculative cache line. The mechanisms also generate the checkpoint (1310) in the speculative versioning cache (310, 1210) in response to a determination that the first condition has occurred.