公开(公告)号：GB2462165A9

公开(公告)日：2010-03-24

申请号：GB0910505

申请日：2009-06-18

Applicant: IBM

Inventor： HELMS MARKUS ,  RIDER SCOTT H ,  TARR GABRIEL MARTEL

IPC: G06F17/00

公开(公告)号：GB2454599B

公开(公告)日：2012-03-14

申请号：GB0822308

申请日：2008-12-08

Applicant: IBM

Inventor： HELMS MARKUS

IPC: G06F11/34

公开(公告)号：GB2462165A

公开(公告)日：2010-02-03

申请号：GB0910505

申请日：2009-06-18

Applicant: IBM

Inventor： HELMS MARKUS ,  RIDER SCOTT H ,  TARR GABRIEL MARTEL

IPC: G06F17/50

Abstract: A method for optimising a hardware design wherein the hardware design is given as hardware description language file using a certain hardware description language code (e.g. VHDL) comprises parsing the hardware description language file of the hardware design into at least one object. The at least one object is analysed to detect an optimisable object, which meets a least one given condition. A first condition is met, when an operation of the analysed object exploits a loop structure, transforming the optimisable object (unbalanced tree) into a new optimised object (i.e. converted into a unfolded parallel structure (see Fig. 4)) which operates a matching recursive algorithm. The new optimised object uses the same hardware description language as the optimisable object, and the new optimized object replaces the optimisable object in the hardware description language file.

公开(公告)号：GB2454598A

公开(公告)日：2009-05-13

申请号：GB0822217

申请日：2008-12-05

Applicant: IBM

Inventor： DORSCH RAINER ,  GRASSI MICHAEL ,  HELMS MARKUS ,  PANDEY KULWANT M ,  SCHLIPF THOMAS

IPC: H04L12/56

Abstract: An apparatus and method is disclosed for transferring data packets synchronously in a credit controlled manner from a transmitter (10, fig. 1, not shown) to a receiver (20,fig. 1), wherein the receiver transfers a credit to the transmitter and the transmitter transfers said packets to the receiver in response to said credit showing available buffer space in a data buffer (26,fig.1) of the receiver. The data buffer (26) is configured to comprise a virtually unlimited buffer space offering infinite credits. The receiver creates a credit signal (CI1, C12, CI3, C14, DC12, DCI3), which shows, independent from a physical size of the data buffer (26), a virtual buffer space giving credit for just one further data packet to be received at a time from the transmitter, and transfers the credit signal to the transmitter, wherein the receiver component sends a credit (e.g. CI1) for a following packet as soon as it starts receiving a current packet, but can delay sending the credit for a certain time (e.g. DC12, DC13) if conditions in the data buffer demand a delay. The delayed credit forces the transmitter to insert a gap (e.g. FG1, FG2) between packets. The timing of the normal credit CI1 ensures that through put is not compromised.

公开(公告)号：GB2454597A

公开(公告)日：2009-05-13

申请号：GB0821855

申请日：2008-12-01

Applicant: IBM

Inventor： HELMS MARKUS ,  SCHLIPF THOMAS ,  SENTLER DANIEL

IPC: H04L1/00 ,  G06F11/10 ,  G06F17/30

Abstract: In the prior art a received packet is stored as a linked list in a buffer memory as blocks 26 at a series of addressed memory locations 24 with pointers 28 to the next memory location. If an error occurs during readout the blocks can be incorrectly chained together, which would not normally be detected until the packet was processed, and some memory locations can be erroneously overwritten. The invention also stores a status flag 30 indicating start/final/only blocks within packet as well as valid/invalid blocks. Each block is also assigned a packet sequence number 32 and a block sequence number 34. By checking these values when each block is read out errors in the linked list can be quickly detected and erroneous deletion of data avoided.